so, for reasons I can't quite recall (I think I was bored), it turns out you can take something like the esp-idf build process, and split the build out across say, a set of arm rockchip nodes with pretty little effort.
practical? maybe not for esp-idf stuff, but it's a fun toy!
Very fun - I had a similar idea, but stopped at lightscribe discs (for some reason)
this project using stock writable CDR media is a huge huge advantage over the pricier LS discs!
https://t.co/06tRFic8e9
@_MG_ no i can see how that would be possible.
i'm actually very curious, can you see your potting compounds outgassing (moreso their breakdown products) over time?
or did you have to spring for non acetic RTVs/compounds?
that's if you are using them anywhere 👀
1/16 You can see inside a circuit board without cutting it open.
Send a fast step into a USB port and listen for the echoes. Every bump is a spot where the layout changes, and its delay says where.
That's TDR, radar for PCBs. I simulated it on a real Raspberry Pi board 🧵
@_MG_ that's a very good point actually, the entire premise of cap sensing on gpio is down to being able to sense this sort of effect - I imagine this actually could be whipped up as a PIO blob on something like the RP23xx right, ideally as some input to the secure bootloader process?
@_MG_ I saw a paper that was experimenting with doing it at the board level, I cant recall how but I imagine you can characterize some elements with a small FPGA sitting on the relevant wires right.
do a bit of "analog boundary scan" on boot, check all your freq's still match?