TSMC Preparing for Full-Scale Mass Production of "Panel-Level Packaging (PLP)" Semiconductors
TSMC is set to go head-to-head with Samsung Electronics using "panel-level packaging (PLP)," a next-generation semiconductor packaging technology. PLP can significantly improve the productivity of AI chip manufacturing, and with TSMC hurrying to ready mass production, a contest for leadership with Samsung Electronics—which entered the market first—looks inevitable.
According to industry sources on the 15th, TSMC is building out a materials, components, and equipment (MCE) supply chain to establish its PLP mass-production system. It is currently in discussions with domestic and overseas MCE companies on equipment investment. TSMC is reported to be planning to begin PLP mass production as early as next year, and this is read as a move in earnest toward that goal.
PLP is a technology in which a semiconductor wafer with circuitry already formed is cut into individual chips (dies) and then packaged on a rectangular panel to produce the finished product. It contrasts with "wafer-level packaging (WLP)," which is performed on a round wafer. When chips are packaged on a circular wafer, the edge regions cannot be completed into chips and must be discarded—meaning lower productivity. Running the process on a rectangular panel instead allows chips to be produced with no wasted area. Based on a standard 600×600 mm rectangular panel, roughly five to six times as many chips can be produced compared with the mainstream 300 mm (12-inch) wafer.
The company holding the upper hand in PLP technology is Samsung Electronics. After acquiring the PLP business from Samsung Electro-Mechanics in 2019, it has built up technical capability by applying PLP to mobile application processors (APs) and power management ICs (PMICs).
TSMC, by contrast, had been passive on PLP, given that it had secured its foundry competitive edge with conventional WLP. But the situation reversed as the AI chip market grew explosively—PLP can increase AI chip output and is also advantageous for realizing large-area AI chips. Accordingly, TSMC began pursuing the PLP business from 2024. It is expected to build and run a pilot production line this year and, following performance evaluation, enter large-scale production around next year. It is also reported to have already secured a global AI chip customer.
As TSMC accelerates toward PLP mass production, competition with Samsung Electronics is expected to intensify further. Samsung, too, plans to expand PLP application beyond its existing APs and PMICs to high-performance computing (HPC) chips such as AI semiconductors. Glass substrates, which are drawing attention as a substrate for AI chips, are also likely to be adopted in this PLP process—a point that suggests a leadership battle between Samsung Electronics and TSMC in the next-generation substrate market as well.
An industry official said, "Not only Samsung Electronics and TSMC, but also global outsourced semiconductor assembly and test (OSAT) companies have jumped into the PLP process market in large numbers," adding that "along with fierce competition, market growth is expected."