ZeroRISC

End-to-end open silicon security, from design through manufacturing to every field update. 🪸

[ZeroRISC @ZeroRISC_]

Pavona Launches Open-Hardware Ecosystem for Secure Chips (IEEE Spectrum) 🪸

https://t.co/HKuaVS5VQA

[ZeroRISC @ZeroRISC_]

Pavona: the open-source ecosystem for composable secure silicon. (launched today!)

https://t.co/BRaI2NBmeF

🪸🪸🪸🪸🪸🪸

Launch members: Analog Devices, Meta, Qualcomm, Winbond, ZeroRISC, Tenstorrent, Agile Analog, CrossBar, Baochip, SIMPLE-Crypto, Oxford, & MPI

[ZeroRISC @ZeroRISC_]

By adapting a clever technique from Filippo Valsorda, we can exploit the structure of ML-DSA to improve our sampling efficiency, getting more precise performance estimates in 10 hardware simulations than we could before in 100.

Take a look at how we made our benchmarks both faster and more precise in our latest deep-dive here:

https://t.co/t1S4AJG5aJ

[ZeroRISC @ZeroRISC_]

Benchmarks are hard. Cryptographic benchmarks are harder. 📊⏱️

New post-quantum algorithms like ML-DSA can be incredibly difficult to benchmark, because their runtimes can vary depending on random values, meaning lots of time-consuming tests are needed to estimate performance.

[Dave McClure @davemcclure]

#Stanford #Taiwan panel
“Tech Challenges + AI-tariff nexus”
moderated by @stevechen @YouTube co-founder + speakers
@TonyW @500GlobalVC
#DominicRizzo @ZeroRISC_
#JonathanLiao @TaiwanGoldCard
cc @StanfordSAPARC

[ZeroRISC @ZeroRISC_]

Performance, versatility, and maintainability can be at odds unless you design carefully.

Take a peek here at our new blog post for the tricks, tips, and tools we use in maintaining the cryptolib cryptographic library: https://t.co/oFhx0Btprn

[3/3]

[ZeroRISC @ZeroRISC_]

Fast. Flexible. Future-proof. Pick three. 📷📷

After sharing how we achieved ~3x performance on core RSA operations, we’re now giving a tour of how our cryptographic library can support a root of trust in everything from IoT to a BMC.

[1/3]

[ZeroRISC @ZeroRISC_]

Expect formal verification, static analysis, modular design–and of course, more performance tricks.

While implementing cryptography can be an easy engineering exercise, implementing production-quality cryptography is not.

[2/3]

[ZeroRISC @ZeroRISC_]

Last week, we discussed the mathematical details of why CRT modular exponentiation works.

Check out Part 2 below for all of the implementation details, from dealing with register pressure to FIPS certifiability!

https://t.co/jik2XDvqzi

[2/2]

[ZeroRISC @ZeroRISC_]

Lighting-fast crypto in pure assembly? 🏎️💨

Building on our post from last week, we’re sharing the technical details behind our 3.43x RSA speedup from implementing Chinese Remainder Theorem (CRT) modular exponentiation in our embedded cryptography library.

[1/2]

[ZeroRISC @ZeroRISC_]

Modular exponentiation is the core of signing & decryption, and we've sped it up significantly. Check out Part 1 of our series for the mathematical deep dive!

https://t.co/bArVZztdry

#ZeroRISC #RSA #Security #Crypto [2/2]

[ZeroRISC @ZeroRISC_]

3.43x faster RSA! 🚀

ZeroRISC just achieved a huge performance boost for core RSA operations by implementing Chinese Remainder Theorem (CRT) modular exponentiation for our embedded cryptography library. [1/2]

[gabe cunningham @gabecunn]

open source silicon enables verifiable security :)

@zeroRISCinc

[ZeroRISC @ZeroRISC_]

Learn how we’re advancing certification-aligned open silicon in @GlobalPlatform’s Trusted Open Silicon Task Force (#TOS): https://t.co/666XCstmQw [2/2]

[ZeroRISC @ZeroRISC_]

ZeroRISC and Rivos implemented FIPS 140-3 compliant OTP zeroization, showing why building for certification early in silicon design is critical, because do-overs are pricey in hardware. [1/2]

[ZeroRISC @ZeroRISC_]

Read the blog post here: https://t.co/OXaeiTsvgG

[ZeroRISC @ZeroRISC_]

This summer, our MIT intern Yeabsira Hawaz dove into open source silicon integration⚡He designed a TL-UL to AXI bridge + AXI AdapterReg, enabling seamless AXI compatibility. Testing, debugging, and iterating paved the way for smoother adoption & real-world hardware innovation🚀

[ZeroRISC @ZeroRISC_]

This summer, our MIT intern Beshr Bouli improved flexibility & memory efficiency in ZeroRISC’s embedded Rust-based secure OS. PIC + a new memory allocator enables dynamic app loading with less downtime & fragmentation. Learn more in Beshr’s blog: https://t.co/9OMKT3QWyR

[ZeroRISC @ZeroRISC_]

Congratulations to our board member Zakir Durumeric, co-founder of Censys, on winning the Industry Leadership award in the 2025 #CyberScoop50! His groundbreaking work continues to shape the future of security. 👏🔒

[CRN @CRN]

Here’s why @DylanOnChips says these are the 10 hottest semiconductor startups of 2025 (so far) 🌶️: @AyarLabs, @AxeleraAI, @CelestialAIinc, @CornelisHPC, @EnChargeAI, @LightmatterCo, @Speedata1, @tenstorrent, @XsightLabs and @zeroRISCinc
https://t.co/xCviAHCwXd