Cardyak

Computer Programmer/Hardware Enthusiast. #SiliconGang Author of CPU μarch Block Diagrams: & μarch Cheat Sheet:

[Cardyak @Cardyak]

Inspired by @InstLatX64, today I'm introducing the #SiliconGang Microarchitecture Cheat Sheet: https://t.co/jMrjm6RfyX

This can be viewed by all, and it offers centralised information about CPU μarch design such as caches, buffers, instruction width, etc.

Some notes below:

[Cardyak @Cardyak]

...instruction window, exposing a new, medium-grained parallelism, orthogonal to traditional ILP and TLP. LoopFrog monitors data dependencies between executing threadlets, forwards data for true dependencies and squashes speculative threadlets on ordering violations.

3/3

[Cardyak @Cardyak]

This is a nice trick called LoopFrog

https://t.co/bX7972RStZ

Using an LLVM-based compiler to insert hints, we achieve a geometric mean loop speedup of 43%, translating to whole-program speedups of 9.5% on SPEC CPU 2017 benchmarks, with only modest area and power overheads.

1/3

[Cardyak @Cardyak]

LoopFrog runs multiple loop iterations from a single thread in parallel within the microarchitecture. The core can spawn future loop iterations as new microarchitectural threadlets based on compiler-inserted hints, which can leapfrog execution beyond the parent thread’s...

2/3

[Cardyak @Cardyak]

@dylan522p Inference ATLAS

[Cardyak @Cardyak]

https://t.co/LbkEqSSjQ1

"SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads"

"dynamically balances ILP and TLP by executing out-of-order and in-order threads simultaneously on the same core"

Could this be what AheadComputing is working on?

#CPU #μarch

[Cardyak @Cardyak]

https://t.co/uc810tQNX8

"ATR: Out-of-Order Register Release Exploiting Atomic Regions"

Interesting μarch idea here. Instructions that have finished execution but not been committed yet, and also do not contain conditional branches can free up their PRF entry early

#CPU #μarch

[Cardyak @Cardyak]

@OneRaichu Great data! Did you manage to confirm if Darkmont or Cougar Cove and handle 2 taken branches per cycle?

[Kurnal @Kurnalsalts]

This Gen Mobile phone SoC size

[Kurnal @Kurnalsalts]

A19Pro with A18Pro area surveying data
A19Pro 与A18Pro的面积测绘数据

[Cardyak @Cardyak]

@boris_dg N3P only offers a 6% density gain, so by default it’s not enough to shrink down from the size you mentioned to 99mm.

There’s more to it than that, especially when you remember the CPU and GPU had extra functionality added which increases the transistor count.

[Cardyak @Cardyak]

Apple A19 Pro die shot

Die Size 98.68mm²
P-Core 2.966mm²
P-Core with L2 & Shared Logic 5.486mm²
E-Core 0.782mm²
E-Core with L2 & Shared Logic 2.217mm²
SLC 11.026mm²

Somehow looks to be smaller than the A18 Pro (~104mm²)

#Apple #iPhone #CPU #A19

https://t.co/OHqDtnIcko

[Cardyak @Cardyak]

@realnvmd They share cores with the A Series SoCs featured in the iPhone. Firestorm is the M1 big core, A19P is the big core in the M5 as well, etc

[Cardyak @Cardyak]

Updated the Apple core diagrams to properly reflect the unconventional ROB structures that are used

Still lots of work to do, I need to separate the dispatch queues from the schedulers and research/confirm the L1 ICache bandwidth

μarch Block Diagrams: https://t.co/cTdkRFDpL1

[Cardyak @Cardyak]

@Frederic_Orange @onrefaitlemac Do you have die size estimates for these chips?

[Cardyak @Cardyak]

@MCH2024 There’s also mistakes on their diagram, the ARM documentation tells us there’s 6 FP execution units, not 5. We know this for a fact.

Also the ROB increased by up to 25%, so it can’t be above 960

[Cardyak @Cardyak]

ARM's new μarches added to the block diagram repo

Scarce info this year, these diagrams will be updated and mistakes corrected once more devices are released

μarch Block Diagrams: https://t.co/cTdkRFDpL1
μarch Cheat Sheet: https://t.co/sUmiiw4Ldw

#ARM #CPU #MicroArchitecture

[Cardyak @Cardyak]

Nice work from @highyieldYT and also @chipwise_tech, wish we had the mm2 measurements to be able to truly compare against the A18 & A18 Pro

[High Yield @highyieldYT]

.@Apple A19 SoC chip analysis based on images by @chipwise_tech: 2 P-cores with 8MB shared L2$, 4 E-cores with 4MB shared L2$, a 8-core NPU (Apple calls it 16-cores), 2x 6MB System Level Cache (SLC) and a 5-core GPU. All on TSMCs N3P and smaller than the previous A18.

[Cardyak @Cardyak]

@divBy_zero @handleym99 @MrMadbrain Interesting confession! I assume it saved enough area to be worth the compromise? How easily do you think ARM can expand the decode/allocate stage to 12 or even 16 wide?

[Cardyak @Cardyak]

Block diagrams for A19 P & A19 E by Apple.

Info sourced by Geekerwan and the Apple Silicon Optimization Guide

μarch Block Diagrams: https://t.co/cTdkRFCRVt
μarch Cheat Sheet: https://t.co/sUmiiw4dnY #ARM #CPU

#ARM #Apple #A19 #CPU #MicroArchitecture

[Cardyak @Cardyak]

@divBy_zero Would love to see them progress to 12 wide soon

[Cardyak @Cardyak]

The IPC for the E Core is so high now, it's only slightly behind the P Core that was present in the A12 (Vortex)