Columbia SLD Group

System-Level Design group at Columbia University led by Professor Luca Carloni (

[Columbia SLD Group @ColumbiaSld]

Happening tomorrow at 11 am! @guyeichler will present his paper "MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain Computer Interfaces" at ICCD'23 in Washington DC

[Columbia SLD Group @ColumbiaSld]

We are thrilled to share that our work "SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs" has received the Best-Paper Award at the 17th IEEE/ACM International Symposium on Networks‑on‑Chip (NOCS'23)!

Check out the paper at https://t.co/l040ejezJs

[Columbia SLD Group @ColumbiaSld]

Check out the list of accepted presentations and posters at OSCAR'23.
Just a reminder: today is the last day for early registration!
https://t.co/idqXV95OTM
https://t.co/oViz5kGuZ1

[Columbia SLD Group @ColumbiaSld]

Congrats @guyeichler on being awarded the Best Presentation at RAGE'23 for the paper "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators"
#RAGE23

[Columbia SLD Group @ColumbiaSld]

We are thrilled to announce that the second edition of OSCAR, the new workshop dedicated to open-source hardware, will be co-located with ISCA in Orlando on Sunday, June 18.
The abstract submission deadline is this Friday, May 5th

https://t.co/8irdWxV2ij

https://t.co/WgXf7gW57s

[Columbia SLD Group @ColumbiaSld]

Join us tomorrow (11 AM) at DATE in Antwerp for a tutorial on ESP! We'll be covering new features like accelerator design with Catapult HLS and dynamic partial reconfiguration of FPGAs!
@DateConference

[Columbia SLD Group @ColumbiaSld]

Looking forward to our tutorial this Sunday! Hope to see you in Vancouver!

[Columbia SLD Group @ColumbiaSld]

Join us in Vancouver for a tutorial on ESP at ASPLOS '23! We'll be covering new, exciting features like accelerator design with Catapult HLS, dynamic partial reconfiguration of FPGAs, and an intro to ASIC design with ESP! Early registration deadline is this Friday.
@ASPLOSConf

[Columbia SLD Group @ColumbiaSld]

Check out the ESP Tutorial page and #ASPLOS2023 Registration instructions!

https://t.co/ePQZveWNXI
https://t.co/e0Z1fd93MD

[Columbia SLD Group @ColumbiaSld]

Join us in Vancouver for a tutorial on ESP at ASPLOS '23! We'll be covering new, exciting features like accelerator design with Catapult HLS, dynamic partial reconfiguration of FPGAs, and an intro to ASIC design with ESP! Early registration deadline is this Friday.
@ASPLOSConf

[Columbia SLD Group @ColumbiaSld]

Join us in Vancouver for a tutorial on ESP at ASPLOS '23! We'll be covering new, exciting features like accelerator design with Catapult HLS, dynamic partial reconfiguration of FPGAs, and an intro to ASIC design with ESP! Early registration deadline is this Friday.
@ASPLOSConf

[Columbia SLD Group @ColumbiaSld]

A new GitHub Release of #ESP is now available: https://t.co/g17rkL3UoU. Check out the release notes for the complete list of #ESP features.
@ColumbiaCompSci

@CUSEAS

[Columbia SLD Group @ColumbiaSld]

Earlier this month, we presented the paper "A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components" at ICCAD 2022.

https://t.co/kBtrJWkxBO
https://t.co/JNY4gcqjqA

[Columbia SLD Group @ColumbiaSld]

Big Milestone for the OSH community: ESP is silicon-proven!

Check out the first chip based on the #ESP platform. This work is a collaboration with Harvard and IBM Research, recently published at #ESSCIRC 2022.
https://t.co/JBbNgImwIb
https://t.co/g2k3uCpK6R
@ColumbiaCompSci

[Columbia SLD Group @ColumbiaSld]

The official program of OSCAR 2022, the new workshop on open-source hardware, is out!
Check it out at https://t.co/I8NrrZSgCw
#OpenSourceHW #ISCA2022

[Luca Benini @LucaBeniniZhFe]

Nice work by the team of Prof. Luca Carloni. By the way, the #riscv processor is @openhwgroup CVA6, one of the @pulp_platform open source cores!

[John Round @openhwsw]

** Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP #riscv https://t.co/758miDGOMW

[Columbia SLD Group @ColumbiaSld]

We will be presenting our work on “Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP” at the Sixth Workshop on Computer Architecture Research with RISC-V #CARRV in NYC on June 19th!
https://t.co/Y4u00bhKal
https://t.co/Rh6C0MY9N3

[Columbia SLD Group @ColumbiaSld]

Luca took part to the Spring 2022 RISC-V Week in Paris with the talk "Open-Source Hardware for Heterogeneous Computing with ESP and RISC-V". For more info on our open-source heterogeneous SoC platform, check out the #ESP website:
https://t.co/2UJwCmA3aD
https://t.co/iWIMWpgHHk

[Columbia SLD Group @ColumbiaSld]

A new GitHub Release of #ESP is now available: https://t.co/uzZiqmpsgS. Check out the release notes for the complete list of #ESP features.
@ColumbiaCompSci @CUSEAS

[Columbia SLD Group @ColumbiaSld]

Guy Eichler (@guyeichler) will present his paper “MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces” at ICCD's Novel Architectures session on Monday 10/25, 12:10–1:10 pm !

[Columbia SLD Group @ColumbiaSld]

Our paper "MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces"
has been accepted at ICCD 2021 ! https://t.co/teO8HyX7WU

[Columbia SLD Group @ColumbiaSld]

Our paper "MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces"
has been accepted at ICCD 2021 ! https://t.co/teO8HyX7WU