Customized Parallel Computing research group

[Customized Parallel Computing research group @CustomParComp]

As part of @sochubfi, CPC successfully taped out a customized TTA-based Digital Signal Processor (DSP). "Beaivi DSP" was fully designed and C-programmed by using the OpenASIP tools developed by the group since the 2000s: https://t.co/6lXURWyKc2 @ITC_TampereUni

[Customized Parallel Computing research group @CustomParComp]

Link to the full playlist: https://t.co/jNPXMfTREB

[Customized Parallel Computing research group @CustomParComp]

The results of past 3 years of hard work on the edge AI offloading SW stack based on PoCL-R were shown in the AISA Y3 demo day last Friday. Feature showcase videos available (spoiler: Crazyflie can edge offload AI!): https://t.co/HWMFq4MfdC @vga_tuni @OpenCLorg @Bitcraze_se

[Customized Parallel Computing research group @CustomParComp]

OpenASIP v2.1 released: https://t.co/AvJPhA6N8X. It adds support for LLVM 17, speeds up DSE thanks to a more intelligent LLVM BE generation, and more! @sochubfi

[Kari Hepola @HepolaKari]

Our article introduces a dual-mode processor that utilizes ILP statically when available, without suffering from low code density when it's lacking. The architecture, supported by a novel compilation method, enables fine-grained mode switching. Read more: https://t.co/IpUSjuAbyG

[Customized Parallel Computing research group @CustomParComp]

Maarten Molendijk from @TUeindhoven presented "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC" in @ieee_iccd. BrainTTA was designed and programmed using the https://t.co/c34lbhNMba tools. https://t.co/mJs1SnqCvT @sochubfi

[PoCL developers @portablecl]

PoCL-R is a new backend for offloading OpenCL tasks to other nodes on the network. Now with OpenCL API offloading can be performed identically whether using local or remote devices - very interesting for adaptive edge offloading and other use cases! https://t.co/PxNIEILekw

[Customized Parallel Computing research group @CustomParComp]

HW accelerators require vendor-specific steps to use. A generic memory-mapped interface helps integrating them to a diverse OpenCL platform. Our interfacing work is now published in https://t.co/w7iS9pXdI9 and the code available in the @portablecl repo! @openclapi @CPSoSAWARE

[Customized Parallel Computing research group @CustomParComp]

Check a demo made with some of our final technical outcomes from the @CPSoSAWARE EU project: Nano-PoCL, PoCL-R and AlmaIF v2. Offloading OpenVX from a nanodrone to an FPGA using OpenCL as the offload API. Exciting stuff! https://t.co/OTiq8zFTlm @openclapi @portablecl

[Customized Parallel Computing research group @CustomParComp]

OpenASIP 2.0 is out! It has the first #RISCV customization features, improved FU generation, LLVM 15, IP wrapping, among other new features! @sochubfi @CPSoSAWARE @openhwgroup https://t.co/CooaApRDPI

[Kari Hepola @HepolaKari]

VLIW processors exploit ILP efficiently but suffer from bad code density in serial parts where instruction packets cannot be fully utilized. Read how we increased flexibility and energy efficiency by using both a TTA and RISC-V based ISA in one processor.

https://t.co/8jRER85GaH

[Kari Hepola @HepolaKari]

The open-standard RISC-V ISA has made the open source hardware community more active but there has been a lack of tools for customized RISC-V processors. Read how we added support for RISC-V based ASIPs to the upcoming 2.0 release of the OpenASIP toolset.

https://t.co/LqB9loShe0

[Customized Parallel Computing research group @CustomParComp]

OpenASIP 1.25 is now out. It supports LLVM 14 and adds partial retargetable inline asm support and loop buffer compilation features. https://t.co/qBktjBeaQi Thanks to @CPSoSAWARE for supporting the @CustomParComp
group's contributions! @sochubfi @llvmorg

[Joonas Multanen @JoonasMultanen]

Emerging memory technologies could enable extremely energy-efficient compute devices in the future. Read how domain wall memories can be utilized efficiently with our SHRIMP method.

https://t.co/15OCaHzloT

@TampereUni @CustomParComp @cfaed_TUD @FitOptiVis @CPSoSAWARE

[Customized Parallel Computing research group @CustomParComp]

OpenASIP 1.24 released! Adds LLVM 13 and first steps for Blocks CGRA support. https://t.co/qBktjBeaQi Thanks @FitOptiVis
@CPSoSAWARE @sochubfi for supporting the @CustomParComp group's contributions!

[Customized Parallel Computing research group @CustomParComp]

A presentation about our ongoing work on PoCL-R: Distributed OpenCL Runtime for Low Latency Offloading available: https://t.co/07FqxAVkfZ @portablecl @openclapi @FitOptiVis @CPSoSAWARE

[Customized Parallel Computing research group @CustomParComp]

CPC is looking forward to contributing to this interesting joint project in its distributed high performance low latency computing aspects!

[DIMECC @dimecc_fi]

Great news! @dimecc_fi facilitates the new AISA (AI based Situational Awareness) project!
The partners of the #AISAPROJECT are @nokia Technologies, @valmetglobal Automation, #Mirka, #Insta, @TopDataScience, @ficololtd and @TampereUni @BusinessFinland

https://t.co/MxQ3itFRBC

[Customized Parallel Computing research group @CustomParComp]

OpenASIP 1.23 released! It's mainly a maintenance release that adds LLVM 12 support and removes support for older than LLVM 11 to clean up the code base. https://t.co/qBktjBeaQi Thanks @FitOptiVis @CPSoSAWARE @sochubfi
for supporting the @CustomParComp group's work!