DaveyPocket

Sometimes electronics

[DaveyPocket @DaveyPocket]

Can now stream arbitrary WAV files to Satellaview base unit: https://t.co/jVpon9Ry91

[DaveyPocket @DaveyPocket]

https://t.co/ctzZvXYkSX

Wish I had known about this type of DIP socket in the past 👀

[DaveyPocket @DaveyPocket]

@antoniovil I don't mind hearing the ideas, my DMs should be open

[DaveyPocket @DaveyPocket]

@antoniovil I don't have familiarity with all of the constraints of the system but I don't see why it wouldn't work at first glance - I am interested in experimenting if I can get more information on what needs to be done.

[DaveyPocket @DaveyPocket]

@antoniovil Interesting - what are the available I/O pins going to the current FPGA board?

[DaveyPocket @DaveyPocket]

@danluu Right before I moved and did not care about a "permanent" setup I used this: https://t.co/c0JmziQJbR

Reflecting against the walls in my apartment. Minor amount visual annoyance if I saw a bit of where the light was coming out of the lamp as it is intense.

[DaveyPocket @DaveyPocket]

@pepijndevos You will need one after you get one - a very useful tool indeed.

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@matthewvenn "Logical Sand Frisbees"

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Near some of the pads

[DaveyPocket @DaveyPocket]

Got access to a microscope, wafer shot of a Mostek MK38P70 microcontroller.

[DaveyPocket @DaveyPocket]

Wafer art?

[DaveyPocket @DaveyPocket]

Made a first attempt at decapping a chip at home using the heating/breaking package method. The process was going smoothly until the plastic did not want to separate from the IC die, so I decided to use an ice pick on the center of the plastic after heating - split the die!

[DaveyPocket @DaveyPocket]

Vintage Xilinx

[DaveyPocket @DaveyPocket]

@OlofKindgren Incorporate Logisim into FuseSoC next?

[DaveyPocket @DaveyPocket]

Also changed out the resistor arrays with individual resistors as I don't have the tools to properly solder the package size for the resistor arrays I originally obtained.

[DaveyPocket @DaveyPocket]

It has been a while since I last worked on this project: Initial power-up of the Satellaview tool seems to work meaning the board I have underneath of the FPGA dev. board doesn't go up in smoke.

[DaveyPocket @DaveyPocket]

Fixed

[DaveyPocket @DaveyPocket]

@furan Chiplets? At least with that Xilinx package it looks like

[DaveyPocket @DaveyPocket]

Blink