Manthan Admane

i observe photons

[Manthan Admane @ManthanAdmane23]

@jaeholeeeee @TTrimoreau You’re 1 success away from your first success
Welcome to the club

[Manthan Admane @ManthanAdmane23]

All conversations are mere extrapolation of a fuzzy reality

[Manthan Admane @ManthanAdmane23]

Is this the “worst” subscription in the world?

If so, you’ve succeeded @Meta

[Manthan Admane @ManthanAdmane23]

@DarrelFrater DM!

[Manthan Admane @ManthanAdmane23]

@DarrelFrater Great article!
Go all in 💯

@DarrelFrater would love to chat more, cheers!

[Manthan Admane @ManthanAdmane23]

@DarrelFrater DM

[Manthan Admane @ManthanAdmane23]

@DarrelFrater Super DM! @DarrelFrater

[Manthan Admane @ManthanAdmane23]

@Spendino_ @Jason This makes no sense.

Two car owners will continue keep the excess convenience irrespective of the cost.

[Manthan Admane @ManthanAdmane23]

@Linds_Erik @Linds_Erik silicon wafer purity is where Pax Silica logic actually starts. Shin-Etsu and Sumco supply 60%+ of semiconductor-grade silicon. sub-nanometer surface precision nobody else has. neither is in any alliance conversation. the input layer runs deeper than the fab.

[Manthan Admane @ManthanAdmane23]

@Linds_Erik ASML's 19% China exposure is roughly 20 of 60 annual DUV machines. strip it and the economics for every other buyer tighten. Netherlands isn't protecting China revenue. they're protecting the unit volume that makes ASML's model work.

[Manthan Admane @ManthanAdmane23]

@i_mika_el @i_mika_el Cadence and Synopsys tracked each other for a decade. 2026: diverging fast. Cadence writing Intel 14A design rules - foundry relationship baked into the tool. Synopsys moving deeper into AI chip verification. EDA is now splitting by fab alignment.

[Manthan Admane @ManthanAdmane23]

@i_mika_el the leverage isn't just the tools. it's the PDK. process design kits are the translation layer between EDA and a specific fab. TSMC's PDK is proprietary. getting access to Cadence doesn't mean you can tape out at TSMC. two separate locks.