Das

[Das @Nota_FaNbOi9]

@Mojo_flyin @realmemes6 @D_K_Rajasekar It's not pure speculation though? Things leak all the time. Plus look at the LTD exodus, much of their top leadership left and many engineers laid off. What could be a clearer admission of failure. Unless 14A miraculously wasn't affected, it's not clear if it'll even launch

[Das @Nota_FaNbOi9]

@D_K_Rajasekar IF's still screwed if ongoing layoffs actually affect process engineering. They had a "blank check" to catch up and still failed to secure a single whale customer. Now either divest or try again later. There'll be lots of complaining but something has to give eventually

[Das @Nota_FaNbOi9]

@G_melo_ding It's probably due to cost. U series using advanced packaging with multiple tiles makes no sense, it should've been a monolithic 150-170mm2 die(like WCL)

[Das @Nota_FaNbOi9]

@G_melo_ding @Silicon_Fly @ChipsandWafers They're laying off fab workers while "shifting away" from copy exactly, how does that make sense... Don't they need way more talent at each fab for their new vision?

[Das @Nota_FaNbOi9]

@Alex_Intel_ @Luce_On_TSLA @howardlutnick @IntelPolicy Bringing tsmc to the US sounds even more enticing that seems to be what they're trying to accomplish

[Das @Nota_FaNbOi9]

@D_K_Rajasekar They're not taken seriously at all, that's all there is to it. If Intel announced a 200B investment, they'll be laughed at. Micron is in the AI race, Intel isn't. If they don't get it together and deliver a viable N2 alternative with 14A-E, that might be it for IFS

[Das @Nota_FaNbOi9]

@Alex_Intel_ Wafer prices don't matter much for high end AI chips, even with substantial tariffs. They'll almost certainly go with N2P or A16, next one they should try to use 14AE

[Das @Nota_FaNbOi9]

@IanCutress Too much leading edge si die area used up by emib phys,

[Das @Nota_FaNbOi9]

@WrenIndian @OneRaichu I think they have until 7A or 5A with improved CFETs but then it's over... That's why it's such a shame 18A wasn't a hit to grab as much mkt share, this well will eventually dry up and then it'll be like Intel during the quad core era except for the entire industry

[Das @Nota_FaNbOi9]

@WrenIndian @Alex_Intel_ @Silicon_Fly Sadly not possible rn... Mobile dislike bspdn, ifs lags tsmc in ULV perf, +think of all the custom IP apple, etc built up over the years. For IFS to be ready for spin off, they must sustain positive cash flow for 2-3y at least. Only once it's done will IFS win over major fabless

[Das @Nota_FaNbOi9]

@realmemes6 Fabless don't want to help Intel out of this hole. IFS needs products to lead, to gain enough mass and be spun off for actual support from fabless. Mobile wafers would've been ideal, but they're probably more difficult to win over due to design difference, IFS lagging in ULV

[Das @Nota_FaNbOi9]

@WrenIndian @Alex_Intel_ @Silicon_Fly Fabless really don't like helping Intel, expect they'll downplay it and minimize wafer deals as possible. Ideally Intel would spin off fabs asap, to get actual support from fabless. Currently mobile would be ideal since they don't compete, but IFS is far behind in ULV I think...

[Das @Nota_FaNbOi9]

@XYang2023 @SquashBionic @Alex_Intel_ Probably not since the falcon shores that recently became an internal test platform was using N3 afaik. I'd expect N2P or A16 for Jaguar as 14A clearly won't be ready in 2027(only starts risk production)

[Das @Nota_FaNbOi9]

@XYang2023 @YouTube This ain't good...

[Das @Nota_FaNbOi9]

@hjc4869 Yes, that's why they need such beefy L2 on P cores... At least with hybrid bonding they should be able to put a lot more L3 on the base tile, and maybe use a central IO tile instead of one giant slow mesh fabric

[Das @Nota_FaNbOi9]

@XYang2023 Foundry Intel/UMC 10 or 7 coming? Intel should be careful to not give away important IP and create yet another leading edge competitor

[Das @Nota_FaNbOi9]

@PetGelsinger @Alex_Intel_ LNC first portable core, I doubt they'd want to port it to i3 just for this occasion

[Das @Nota_FaNbOi9]

@OneRaichu Is mobile -h on IFS at least? Or only Non K dt like the original ARL?

[Das @Nota_FaNbOi9]

@OneRaichu They still chose N2 for top NVL meaning even 18A-P(+5-10% perf v. 18A) isn't close to N2. DMR on 18AP might be at a disadvantage v. Zen 6

[Das @Nota_FaNbOi9]

@SquashBionic @G_melo_ding @Olrak29_ Some FCS, ucie diagrams Intel's been sharing and there was some old rumor that mentioned 4 base tiles. Would be a cool looking CPU with 4 base tiles in SPR fashion and small compute chiplets stacked stacked on top