RandomStyuff

A programmer with ADHD who hyper-focalizes on his ever-expanding interests and hobbies (including hardware, graphics, robotics, food, painting, philosophy, ...)

[RandomStyuff @RStyuff]

@CapFrameX Is this based on @lamchester 's PMC Reader?

[RandomStyuff @RStyuff]

@lauriewired @idoccor No problem.

At 400mhz I can do it in 4 cycles

[RandomStyuff @RStyuff]

@GenAI_is_real The effect of ARM vs x86 is negligible for RAM capacity, the OS has a substantially bigger impact. If a program allocates x pages for data on x86, it will allocate the same X pages on ARM: the datatypes are the same size.
Code (.text) pages would be different but very close size.

[RandomStyuff @RStyuff]

@AgileJebrim Not that I'm aware of but it's very possible something like that exists that isn't externally documented or maybe even is and I'm not aware of it

[RandomStyuff @RStyuff]

@AgileJebrim That means that as long as you have decent memory (and AMD's memory controller is decent), you should have at least an anti-starvation level of bandwidth (DDR5 5600 should get close to 90GB/s, 6400 should get around 100GB/s).

[RandomStyuff @RStyuff]

@AgileJebrim At the end of the day, as long as you share a memory controller there will be some competition and arbitration.

Here you kind of would benefit from AMD's disadvantage though: CCXes are connected to the fabric through a thin pipe that saturates at ~70GB/s.

[RandomStyuff @RStyuff]

@AgileJebrim Here it's going to the limits of my knowledge of AMD's uarch but I assume that if you don't ask for the pages to be coherent with the CPU the GPU driver should make it so that it's not a problem.

[RandomStyuff @RStyuff]

@AgileJebrim Yes, it is also probably for the better for most uses, because otherwise your L3 would get dirty really fast with lots of data that your CPU cores don't need.

[RandomStyuff @RStyuff]

@AgileJebrim The BW would likely even be worse than memory BW, because the CCX interface is limited, and I assume this will only happen for data that was modified by the CPU and then accessed as coherent by the GPU.

To be honest even then it's possible AMD would just do a write back to DRAM

[RandomStyuff @RStyuff]

@AgileJebrim Yeah, it's wrong in the ways that matter.

The iGPU doesn't allocate to the L3, but in all cases, if the line is jn the L3 (because the CPU cores read it or wrote it), it's possible it can read from the L3.

Not sure if you'd even see a latency or BW benefit (most likely not)

[RandomStyuff @RStyuff]

@AgileJebrim In Mobile they don't have a separate CCD but logically there is still no change: they don't allocate to the CPU's L3 from the GPU.

[RandomStyuff @RStyuff]

@AgileJebrim To my understanding, servers don't currently have any iGPUs unless they are the desktop sold as server variety.

[RandomStyuff @RStyuff]

@AgileJebrim I'm sure there are better places that document it too.

Also, if you control hardware choice and don't need a powerful CPU (or very specific IO requirements) the low end mobile SOCs have better iGPUs, and Intel's iGPU is also pretty good for compute tasks (especially recently)

[RandomStyuff @RStyuff]

@AgileJebrim I'm not at my computer but if you look at the dieshots here https://t.co/8DfIi38sSe
You can see that there's no room in the CCD for iGPU and that iGPU components are on the IO Hub die.

It's also documented in this chipsandcheese article at the end https://t.co/PDCVi3DdC3

[RandomStyuff @RStyuff]

@AgileJebrim On desktop AMD added their iGPU to their IO hub die, not the CCD. If I had to guess, part of it is that the die size was defined by how much shoreline (perimeter) they needed so they had room in the middle to add logic for almost free.

[RandomStyuff @RStyuff]

@NeubaumResearch @EconomyApp I believe it's due to how much of the IFS revenue is actually internal from inside Intel, so it's an income to Foundry but expense to the client and data center groups

[RandomStyuff @RStyuff]

@hkultala @ChipsandCheese9 I would assume that the CPU still does lookups in it but doesn't allocate into it, in which case it would still be a memory side cache

[RandomStyuff @RStyuff]

@Silicon_Fly @ShakeP2E They didn't share those details in the lunar lake tech tour either, I think they intentionally split technology from productization details.

[RandomStyuff @RStyuff]

@IanCutress @TheGameBench @iDeco_UK @IceStorm Technically it's not a chicken bit for that, chicken bit is to toggle a feature or change off in case of an issue (chicken as in fear).
For overclocking you use fuzes, not unlike houses/cars used to have that you blow when overclock is used. No functional affect but detectable.