Adam Greig

🚀; also electronics, RF, signal processing & comms, embedded and scientific software, FPGAs, Rust. He/him. 🦋 @agg.io

[Adam Greig @adamgreig]

@lethalbit thanks for the tip, that's great! sure beats `size -A`

[Rust Embedded Working Group @rustembedded]

📣 Hello all! The 2024 Embedded WG Survey is now live!

https://t.co/JKJ8brn7KJ

We'd like to hear about your use of Rust on Embedded Systems, and you can help us by taking this anonymous survey, run by the Rust Survey team.

CC @rustlang - and all other RTs/shares appreciated!

[Adam Greig @adamgreig]

@GregDavill Is it worth upstreaming? I don't think I've seen that command for other flashes but it could conceivably run it based on chip ID.

[Adam Greig @adamgreig]

@softminus Oh yea, we have this in the tape box at work, it's a bit worse for wear though.

[Adam Greig @adamgreig]

@tom_verbeure Even the fancy newer Keysight PSUs have a power-on voltage spike, originally bad enough for a recall, I was getting 8V for 300ms while after the fix it's 6V for 200ns into a 2R load

[Rust Embedded Working Group @rustembedded]

📣 Heads up! `embedded-hal` has released 1.0.0-rc1! This release candidate is intended to be the "last check" before the 1.0.0 version is finalized.

If you maintain a HAL that impls e-h traits, or a driver that uses them, please test it ASAP!

https://t.co/TG30KOOLqa

[Adam Greig @adamgreig]

@lapsansou Yea shame! We did, worth having to drive in for :)

[Adam Greig @adamgreig]

While I still numerologically hope Twitter makes it to July so it's a round 15 years since I signed up, if you're sensibly setting up alternatives you can also find me at @[email protected] or https://t.co/ojHKwMtniM.

[Adam Greig @adamgreig]

@attiegrande @tom_keddie Could it be getting a little phantom power from the debugger I/O? Is it still lower after you physically disconnect the debugger?

[Adam Greig @adamgreig]

and, it turns out loading a bitstream to SRAM that has an SPI_MODE command causes an abort if the SPI flash doesn't already contain a valid bitstream (??), so ecpdap will now also remove those commands when loading to SRAM. works with any cmsis-dap probe, give it a try!

[Adam Greig @adamgreig]

ecpdap (ECP5 FPGA programmer, https://t.co/hUUUIxflQx) 0.2 now out, with live patching bitstreams to fix compatible IDCODEs, which is great when stock shortages means you have a whole mix of compatible ECP5s and don't want to manage a ton of bitstream variants!

[Adam Greig @adamgreig]

@attiegrande https://t.co/OBtkoh4Skk looks like it has some nice diagrams and talks about all these issues, might be a good place to start!

[Adam Greig @adamgreig]

@attiegrande yea, you actually measure two voltages/magnitudes, one per ADC, and the I ADC tells you the x part and the Q the y part, giving x+iy, but you can represent that as a magnitude+phase instead

[Adam Greig @adamgreig]

@attiegrande the SDR aspect is slightly complicated because you're downconverting the RF signal by mixing it with a local oscillator, and for IQ you have two local oscillators at the same frequency but 90' out of phase, and then you sample the mixed product at the same time on both ADCs

[Adam Greig @adamgreig]

@attiegrande yea! an IQ sample is a complex number, in other words a point on a plane, so you can represent it as either rectangular form x+iy (distance along each axis) or polar form with mag and phase (distance and angle from origin), and it's the same point either way

[Adam Greig @adamgreig]

@attiegrande and it's about right; you could run one ADC at twice the sample rate to get twice the bandwidth too (but it would start at 0Hz, so you'd have to offset the centre frequency down to get the same chunk of spectrum), but it's cheaper to have two ADCs at Fs than one ADC at 2*Fs

[Adam Greig @adamgreig]

@attiegrande ...I don't know how much that's in "simple terms" though! conceptually you could imagine "two ADCs, so we get twice the bandwidth, one sampling above the centre frequency and the other sampling below it"