Arduissimo

RISC-V 32-Bit project. System Hyper Pipelining, Dynamic Multithreading, Wave-Pipelining, MultiCore Arduino on FPGA and ASIC, Virtual Peripherals.

[Arduissimo @arduissimo]

It is with great pleasure to announce the release of the open source Arduissimo project on github.

Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programs on the ARTY board (XC7A35T).

#riscv #shp #cubev

https://t.co/YlrlrDFdJF

[James Waples @jam_waffles]

How about giving this one a quick sponno, or just a star if you're feeling alternative? A fully open source Rust EtherCAT controller😎

https://t.co/Y39Rup0hZU

[mjos\dwez @mjos_crypto]

Oh, the NIST PQC Draft standard PDFs are out!
FIPS 203 ipd: Kyber (ML-KEM): https://t.co/X6X3bitv8M
FIPS 204 ipd: Dilithium (ML-DSA) https://t.co/0wqbYiSdq8
FIPS 205 ipd: SPHINCS+ (SLH-DSA): https://t.co/uBCRhIzC2n

[Frans Skarman ([email protected]) @TheZoq2]

Made some updates to my #riscv in Spade :) Now it has memory mapped HDMI output, runs rust, and uses Spade's dynamic pipelines for stalling and flushing.

It is also the first Spade project to not use a Verilog top module. No more error prone Shims🎉

[Arduissimo @arduissimo]

@JBalkind Congratulations, looks awesome. Loving it. I also think that processor cluster based simulation solutions can outperform today's commercial emulators.

https://t.co/CJbSpDiwIK

[Arduissimo @arduissimo]

@suarezvictor Thanks, can't wait for the silicon.

[Arduissimo @arduissimo]

@heppoko_yuki Congratulations. Can't wait to see my chip blinking as well.

[Arduissimo @arduissimo]

@tubechip404 Sure, but the solutions depend on the requirements, right? I built the same board for a local Max Planck Institute 10 years ago and the physical connection was crucial. Just a suggestion because I thought it was for sale.

[Arduissimo @arduissimo]

I was looking for inspirations for my wave-pipelining RISC-V project, and found a paper on wave-pipelining in superconducting quantum computing, well, why not.
https://t.co/XlLvfIjuNs

[Gregor vom Scheidt @GregorVScheidt]

I posted a paper on arXiv that shows that GPT-4 has a deep and comprehensive understanding of mathematical logic and functional languages. But this paper has a twist. https://t.co/461UfYuBYp

[Arduissimo @arduissimo]

@Underfox3 How often would you be "... using three predefined IP blocks for signed, unsigned and mixed multiplication, ..." [sentence 2 in abstact] ???

All code I've seen uses one "IP block" or one *, so what ?

[Arduissimo @arduissimo]

@OttatiFabrizio Very informative ... even I understand a little bit. A lot of people dreaming about this for decades. In case I just didn't see it in the paper, any plans to combine it with @mguthaus wonderful OpenRAM work and skywater 90 \ efabless tapeouts ?

[Arduissimo @arduissimo]

@jangray Yes, very nice.
Also very nice: the complete ASPLOS 23 proceedings are free (prop for a limited time)

[Arduissimo @arduissimo]

@asbradbury @risc_v I said recently that I miss your excellent summaries. I look forward to more great blogs from you.

https://t.co/jGQ1XsM9y1

[Arduissimo @arduissimo]

I really miss the days when Alex created the excellent real-time, ad hoc summaries of RISC-V events. #RISCV ambassadors, attendees, OS-enthusiasts, please share some exciting takeaways from last week's #RISVsummit ? What happened that wasn't covered by all that marketing slides?

[Arduissimo @arduissimo]

@notypes Congratulations !

I checked the Calyx page and I see many similarities to my language suggestion PDVL (see below). I hope to meet you one day on one of these conferences to talk about it.

https://t.co/xYMlF86LFt

[Arduissimo @arduissimo]

2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 10,11,12 2023. Submissions are open.

https://t.co/17gmKeFoTA

[Arduissimo @arduissimo]

@efabless @ArtScott4209339 Just follow @Underfox3 He reports about all these fantastic research papers:
https://t.co/fajWwj6dsk

[Underfox @Underfox3]

In this paper, researchers have proposed PDPU, an open-source, a fine-grained, 6-stage pipeline posit dot-product unit with fused and mixed-precision properties.

https://t.co/Xp60ZUx0aM

[Arduissimo @arduissimo]

@dhdezr73 I sincerely hope that you will enlighten us with a paper about your work one day. Also worth a high profile FV conference submission such as HVC etc.

[Arduissimo @arduissimo]

@thoefler When you are talking about a dynamic-interleaved multi-threaded RISC-V as the programmable element, then the answer is definitely yes.

[Arduissimo @arduissimo]

Been there. It's actually very similar.
Unfortunately, as designs get larger, these solutions tend to face the classic memory wall far too quickly. But certainly the right direction in an exciting field of research.
https://t.co/hVi5aItb0i

[Underfox @Underfox3]

Researchers have developed an architecture for parallel RTL simulation which leverages a static bulk-synchronous parallel execution model that virtually eliminates dynamic overheads of RTL simulation through static scheduling.

https://t.co/hjPm0I1a8V