10 stocks to watch during Computex 2026. These are key data centre related stocks :
$MU โ HBM4 36GB delivering 2.6x inference throughput; memory bull case just got louder. ๏ฟผ
$MRVL โ Jensen called Marvell the next trillion-dollar company; CPO chips confirmed future.
$VRT โ Rack power hitting 180kW; Vertivโs power and thermal management demand accelerating fast. ๏ฟผ
$LITE โ Named as relevant across optical modules and fiber alongside Coherent; CPO wave rising. ๏ฟผ
$ARM โ RTX Spark is Windows on Arm; Nvidia just validated Armโs PC architecture ambitions hard. ๏ฟผ
$AAOI โ Makes optical networking components (lasers, transceivers) for data centers and telecom.
$AOSL โ Designs power semiconductors (MOSFETs, gate drivers) for consumer electronics and EVs.
$POWI โ Makes energy-efficient power conversion ICs for appliances, IoT, and industrial use.
$GLW โ NVIDIA partnership locks Corning into AI factory fiber supply; 10x US manufacturing capacity. ๏ฟผ
$ANET โ Capturing majority of 800G and 1.6T switch upgrades as AI clusters shift to open Ethernet-over-Fiber. ๏ฟผ
$ON โ No direct Computex presence found. ON Semi is a Computex spectator, not a headliner.
AI Needs Energy. From Uranium to Cooling: The Power Stack Behind AI ๐งต
Goldman Sachs now sees data-center power demand rising 220% by 2030 vs. 2023, adding 905 TWh. Morgan Stanley sees U.S. data-center demand reaching 74 GW by 2028, with a 49 GW power-access gap.
AI energy map: $CEG $VST $GEV $VRT $ETN $NEE $SMR $OKLO $BE $PWR. ๐
Key stocks in the data centre value chain. Ai canโt run without them
$AMD โ CPU compute for AI training and inference
$VRT โ Cooling and power delivery for dense GPU clusters.
$MU โ HBM memory; feeds data to GPUs at speed.
$SNDK โ NAND flash storage for datasets and model checkpoints.
$ANET โ High-speed ethernet switching between servers and GPUs.
$NBIS โ Deploys and operates GPU clusters as a service.
$IREN โ Cheap-power GPU hosting; miner pivoting to AI compute.
$VST โ Grid-level power generation feeding data centre demand.
CPU vs GPU vs TPU vs NPU vs LPU, explained visually:
5 hardware architectures power AI today.
Each one makes a fundamentally different tradeoff between flexibility, parallelism, and memory access.
> CPU
It is built for general-purpose computing. A few powerful cores handle complex logic, branching, and system-level tasks.
It has deep cache hierarchies and off-chip main memory (DRAM). It's great for operating systems, databases, and decision-heavy code, but not that great for repetitive math like matrix multiplications.
> GPU
Instead of a few powerful cores, GPUs spread work across thousands of smaller cores that all execute the same instruction on different data.
This is why GPUs dominate AI training. The parallelism maps directly to the kind of math neural networks need.
> TPU
They go one step further with specialization.
The core compute unit is a grid of multiply-accumulate (MAC) units where data flows through in a wave pattern.
Weights enter from one side, activations from the other, and partial results propagate without going back to memory each time.
The entire execution is compiler-controlled, not hardware-scheduled. Google designed TPUs specifically for neural network workloads.
> NPU
This is an edge-optimized variant.
The architecture is built around a Neural Compute Engine packed with MAC arrays and on-chip SRAM, but instead of high-bandwidth memory (HBM), NPUs use low-power system memory.
The design goal is to run inference at single-digit watt power budgets, like smartphones, wearables, and IoT devices.
Apple Neural Engine and Intel's NPU follow this pattern.
> LPU (Language Processing Unit)
This is the newest entrant, by Groq.
The architecture removes off-chip memory from the critical path entirely. All weight storage lives in on-chip SRAM.
Execution is fully deterministic and compiler-scheduled, which means zero cache misses and zero runtime scheduling overhead.
The tradeoff is that it provides limited memory per chip, which means you need hundreds of chips linked together to serve a single large model. But the latency advantage is real.
AI compute has evolved from general-purpose flexibility (CPU) to extreme specialization (LPU). Each step trades some level of generality for efficiency.
The visual below maps the internal architecture of all five side by side.
๐ Over to you: Which of these 5 have you actually worked with or deployed on?