damageboy

Making the world a better place through page tables
Works at #5700FF
Pronouns: Has/Been

[damageboy @damageboy]

My vectorized sorting extravaganza is out and about.

A LOT of work went into this (referring to the javascript in the posts :)

Read, retweet, send scathing reviews, open issues, heat your house with it:

This goes to Eleven!

Pt. 1-3, code, nuget out:
https://t.co/U961XhZA3r

[damageboy @damageboy]

@magnus_trent @fardeentwt As IPO season approaches, they will have to kill any non API plans for coding/work.

See the latest msft changes starting June 1st.

[damageboy @damageboy]

@magnus_trent @fardeentwt Which is why the $200 plan will never survive long term with these guys

[fardeen @fardeentwt]

Uber engineers trying to code after the $1,500 token limit ends

[damageboy @damageboy]

TIL that gcc takes the neon garbage on the left and turns it into what's on the right, but clang doesn't:

meh

[damageboy @damageboy]

@serpent7776 @plankers Presumably the lifetime cumulative occurrence of data loss?
I kid. Never tried it myself.

[damageboy @damageboy]

Sometimes these agents are really ungrateful for all the help we give them as they try to do our job:

[damageboy @damageboy]

@hthieblot Fravia

[damageboy @damageboy]

Want one!

[Sascha Segan @saschasegan]

Now this is cute! Finally got hands on with the @Snapdragon X2 Elite powered Asus Ascent QN10 mini PC! Nice solid body, good selection of ports, compact form. This could definitely fit in my home lab.

[Sascha Segan @saschasegan]

Now this is cute! Finally got hands on with the @Snapdragon X2 Elite powered Asus Ascent QN10 mini PC! Nice solid body, good selection of ports, compact form. This could definitely fit in my home lab.

[damageboy @damageboy]

@NBhgdrh עד כדי קיום המדינה ב2045 :)

[damageboy @damageboy]

@csinco @KooKiz @antigravity @AndroidStudio I know, that's what my original post said/asked?

[damageboy @damageboy]

Outside of antigravity, has anyone else (Claude/Codex/pi) implemented a plan "review" mode where I can high light text in the plan file (.md file) and add specific comments pertaining to that part of the plan, them submit it all in one go, a bit like PR review, but for plans?

[damageboy @damageboy]

@insane_analyst so the positron story wrt lpddr5x, is what? That everyone is stupid and can't utilize HBM > 30% but they get lpddr6 to 90%?

Why would hbm utilisation be so low? that is just a hand wavy claim I don't understand. Where is the real world data that supports this?

[damageboy @damageboy]

@efrapinus Then I failed to use it

[Nitay Perets @nitayp]

Happy pride month 🏳️‍⚧️🏳️‍🌈 🌈 ✨ 💖 💜 💙 💚 💛

[damageboy @damageboy]

@SebAaltonen Can you explain/link about their display latency issues? news to me?

[damageboy @damageboy]

@FUZxxl @zetalyrae Sing me the song of my people.

Jokes aside, that is a very clear place where data flow parallelism pulls ahead.

You tape over the unavoidable latency with to s of untethered (to each other, to warps) threads that are free to progress.

But yeah, different game all together.

[damageboy @damageboy]

@FUZxxl @zetalyrae I also think it's not unique in that respect, many instructions fall to this "could've/should've" group but COU designers don't have clear insight to what optimization would lead to greater use in the years after

[damageboy @damageboy]

@FUZxxl @zetalyrae I don't think the problem is memory per-se.
A modern arch with 3 load + 2 store ports, for example, is already structured for parallel accesses to L1, and even to the same line, every cycle.

The sadness surrounding gathers is lack of determination to optimize it specifically

[damageboy @damageboy]

@FUZxxl @zetalyrae Gather is the killer of joy, it runs so badly even when everything is cached in L1 in every impl I know.

Had they built it, we would come...

[damageboy @damageboy]

@valmont100 @Gilshely