2x Baseboards (the final ECOSCALE platform) powered up! 64 FPGAs tightly interconnected & ready to perform acceleration tasks. Each baseboard hosts 8x QFDBs, so the platform gathers 16 QFDBs, with a total of 64 Xilinx Zynq Ultrascale+ MPSoCs and 1 TByte of distributed DDR memory!
The Intel AIB is a die-to-die interconnect standard that speeds development and improves performance. Here’s how it’s promoting chiplet adoption: https://t.co/gWHo481M2C
.@DARPA recently unveiled its first SSITH prototype that uses open source @risc_v cores. The program aims to release 15 different prototypes ranging from low-end IoT devices to high-end systems. Check out this article at @TechTarget to learn more: https://t.co/LjjhkpJClL
Neural nets for AI are limited by slow processing and their need for extensive computing resources. Now two groups have demoed all-optical neural networks that do all processing with light, making neural nets faster and more energy efficient. #ai https://t.co/c0jJARWker
MIT Researchers built a 16-bit carbon nanotube-based microprocessor that can execute the full RISC-V instruction set
The 14,000-transistor chip executed a classic Hello World program
https://t.co/KmXLVfzOYc
The @upscale_project faces the challenge of demonstrating that #AI can also deal with real industrial simulation models, such as full size vehicles, aerodynamics or crash to enhance the design process of #ElectricVehicles! Discover how 👉https://t.co/F9jBBq46wC #WAIC2019#ML#EVs
ICYMI: Watch 👀 the video of the latest in the monthly #HPC Best Practices Webinar Series from the IDEAS Productivity project for ECP: Software Management Plans in Research Projects. Presenter Shoaib Ahmed Sufi of the Software Sustainability Institute https://t.co/uVGbUqwoUp
(Lucky) Blade #13 has been installed in the HPC rack testbed of @ExaNeSt_H2020 as we are getting ready for our final project review.
https://t.co/t4hxVcsyWw
.@AllAboutCircuit spoke with @teodoroj, interim director of the @CHIPSAlliance, to discuss how the Alliance aims to “collaboratively create hardware and open source development tools for the masses.” https://t.co/eKiINNXqHE
An industry & program first! Under our 3DSoC program, the first monolithic 3D device structures produced in a fab were unveiled yesterday at our #ERISummit by Dr. Max Shulaker of @MIT.
https://t.co/aRlsLPfSXt
ECP's Center for Efficient Exascale Discretizations helps applications leverage future architectures by developing state-of-the-art discretization algorithms that better exploit the hardware and deliver a performance gain over conventional methods. https://t.co/4vGpxJXRDm
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