FonTamSOC

RISC-V RTOS-enabled multi-core SoC using Wishbone4 Interconnect.

[FonTamSOC @fontamsoc]

Now using Claude AI

[FonTamSOC @fontamsoc]

@splinedrive https://t.co/uCsOvpdLDO

[FonTamSOC @fontamsoc]

@zipcpu @enjoy_digital Litedram is a great alternative; in this NexysVideo project, RAM controller usage is only 4997.

[FonTamSOC @fontamsoc]

@splinedrive This is what I used to use with my NexysVideo:
https://t.co/8zBhZJrXSe

The same repository has generated controllers from LiteX for: Genesys2, NexysA7, OrangeCrab.

[FonTamSOC @fontamsoc]

@splinedrive Nice! A bare-metal RTOS is much better suited for embedded applications on FPGAs.
Take a look at the RTOS I am developing:
https://t.co/HWRz7rBECx

[FonTamSOC @fontamsoc]

@GregDavill Is OrangeCrab still being manufactured ? it has become un-available for purchase.

Are you working on an upgraded version ? if yes, my feature request would be to make it possible to turn off or control the really bright LED that shows it is powered on.

[FonTamSOC @fontamsoc]

This release now includes the data-cache coherency feature, which greatly benefits multi-core performance, with CoreMark/MHz scaling almost linearly from 1 to 16 cores.

Check out the underLineOS API reference:
https://t.co/HWRz7rBECx

[FonTamSOC @fontamsoc]

Release 20260524
https://t.co/QUVIsI0HzK

[FonTamSOC @fontamsoc]

Software-Hardware Co-design example on OrangeCrab, where a simple hardware peripheral to drive an LED and sample a push-button state is connected using Wishbone4 and driven by software.
_underLineOS multi-threading is used to generate PWM signal and smoothly blink an LED.

[FonTamSOC @fontamsoc]

This release still lacks the data-cache coherency feature which is now passing all tests, but needs loose ends tied before it can be published.
This release is meant for publishing all the fixes and improvements accumulated while working on the data-cache coherency feature.

[FonTamSOC @fontamsoc]

Release 20260422
https://t.co/vwKqyGGCzJ

[FonTamSOC @fontamsoc]

The implications are that atomic variables must always be manipulated by atomic instructions which do not create/update cache-entries, in order to maintain coherency.

[FonTamSOC @fontamsoc]

Fighting cache coherency bugs involving atomic operations.
Atomic operations work using a lock signal that allows a core to have exclusive bus access until the lock is removed. For performance the lock is held for as short of a period as possible.

[FonTamSOC @fontamsoc]

Holding that lock while waiting for coherency traffic would impact performance; hence atomic operations do not use coherency traffic nor does it create/update cache-entries.

[FonTamSOC @fontamsoc]

Fun fact: _OS (underLineOS) is tickless. Timer interrupts are scheduled dynamically whereby the next timer interrupt is programmed based on the nearest upcoming event (thread wakeup, deadline, etc...). It reduces CPU wake-ups, improving power efficiency.

[FonTamSOC @fontamsoc]

@yacineMTB https://t.co/Qlah7R84vS

[FonTamSOC @fontamsoc]

My implementation is an update based cache coherence protocol resembling the Dragon Protocol.
The data-caches of each core are daisy-chained in a circle using valid-ready handshakes/connections through which the coherency traffic circulate.

[FonTamSOC @fontamsoc]

For the past 6 months, I have been working on cache-coherency.

[FonTamSOC @fontamsoc]

You need cache coherency if you have more than one CPU, you want each CPU to use data cache, and you do not want to do manual data cache maintenance (ie: invalidate , writeback) to achieve coherency when accessing data shared by more than one CPU.