Matt Thompson

“The measure of intelligence is the ability to change” -Albert Einstein

[Matt Thompson @fuzziphy]

@tokifyi Nice! I’ve been all of the above, but I’m in a more exploratory/experimental stage right now looking at physical compute (reservoirs, hopfield, hebbian, analog)

[Matt Thompson @fuzziphy]

@robin7331 @seveibar That would be nice.. also wish I had a pnp for my bins full of cut tape parts.

There are some other ways to do vias with solder paste or silver ink, but that sounds like even more work..

[Matt Thompson @fuzziphy]

Onto the worst part of milled PCBs. Dropping in 0.4mm via pins.

[Matt Thompson @fuzziphy]

Doing some CAD for the next board.. laying out a carrier module with some 16x8 analog crosspoint switches routed to PCIe x1 connectors. This will create a 16 wide analog bus that can swing from -5 to +5V and the crosspoints can be controlled from the FPGA to connect any of the 8 inputs of the switch onto any of the 16 lines of the bus.

[Matt Thompson @fuzziphy]

@BurnZeZ @abdimoalim_ Yeah.. there is no such thing as “lock free” on a shared resource. There has to be arbitration, and something has to yield regardless if you call it a lock or not.

[Matt Thompson @fuzziphy]

@Ascion_Next Experimentation in things like nonlinear dynamic systems, evolving state spaces, chaos, but under repeatable digital hybrid control of initial conditions/perturbations and readout

[Matt Thompson @fuzziphy]

Done. Continuity checked out, and all power rails came up.

This brings 36 IOs from an FPGA split into two PCIe edge connectors along with bipolar +/-12V, 5V, 2.5V, and single 3v3 rails. All the IOs to the FPGA have Schottky clamps to prevent accidental overvoltage from the higher voltage rails.

I’ve been experimenting a lot with analog interfaced to FPGAs, and this allows milling edge connectors on experimental PCBs that can plug into the sockets, and provide an array of clean bipolar power rails.

Why all the power rails? A lot of older analog parts like 4Q multipliers want at least +/-9V. Many opamps like TL07x JFET which I like for their extremely high input impedance (Gig ohms) aren’t rail to rail, so you want headroom on the supply. Meanwhile modern fast opamps like TLV354x only work at +/-2.5V. Then there’s crosspoint switches like the 16x8 CH446Q which is +/-5V.

And of course the FPGA digital side itself which is 3.3v.

Now to mill something to plug in… I already have my 8CH DDS DAC that will plug direct into PMOD, but I have some 8 channel SPI DACs that I want to start adding for slow DC control voltages

[Matt Thompson @fuzziphy]

@Giridhar_Raju They’re 0.4mm pins with a flat head on one side. Push them in with tweezers and solder both sides

[Matt Thompson @fuzziphy]

Vias installed

[Matt Thompson @fuzziphy]

I’ve used them on piezos before and they are definitely a pain to not have them just rail from stray charge without a bleed resistor. I went with a charge amplifier and I think a 50Mohm bleed resistor.

It’s pretty interesting to play with floating GOhm inputs though. I was experimenting with some PET sheets suspended between two copper boards with arrays of floating pads milled into them, so it’s like a matrix of coupled capacitors. When you excite different cells with a signal generator or environment (vibration, sound), it influences the whole array but the bias is affected spatially. Memory on plastic.

[Matt Thompson @fuzziphy]

You’d still need the whole analog frontend, FPGA, and RAM which is the bulk of the cost and complexity of a bench scope. Even my 4 channel 2GSa/s Siglent is processing 100Gbps. PCIe isn’t ideal for direct realtime capture because it’s packetized with high latency and arbitration .. plus OS scheduling. Modern computers struggle with audio half the time lol

[Matt Thompson @fuzziphy]

I do have an Arty A7 100T, and an STLV7325. I don’t find openxc7 to be stable enough yet compared to trellis though (specifically DDR).

The one thing I like about the agilex 3 is it has simple SDR x32 RAM, so you can use LiteDRAM without a softcore for DQ/DQS delay training as I’m using no softcore, liteeth for streaming, etherbone for CSR control, and I want to add some deep FIFOs for capturing comparator edge timestamps and spike train similarity search

[Matt Thompson @fuzziphy]

@ico_TC My current dev is ECP5+yosys/trellis+litex on a Lambda ECPIX-5. (This was bringup of custom PMOD board for DDS PDM DAC). I use my ECPIX-5 for other stuff, and they’re unobtanium. Wish I could find more of them.

[Matt Thompson @fuzziphy]

It can’t really in practice at least with any certainty outside of maybe short range, directional, and with huge amounts of energy. EM power density falls proportional to inverse square of the distance (1/r^2), and that needs to couple into something sensitive on the target. A high enough voltage/current would need to be induced to cause physical damage. Only some of energy present in the field is actually coupling, and can be mitigated by simple shielding or protection circuitry. Strong fields aren’t necessarily damaging to electronics at all. It’s mostly SciFi LARPing

[Matt Thompson @fuzziphy]

@zackslab @haydendevs Lorenz! They look so nice on a proper CRT

[Matt Thompson @fuzziphy]

@i2cjak @D_N_K In quantity they do. They’ve sold like 70 million pi’s. An extra 10 cents per board is $7M

[Matt Thompson @fuzziphy]

That’s not a proper debounce circuit either. It should be an RC circuit with a resistor to control the discharge rate and it would charge through the pull-up (I assume the MCU has internal pull-ups?). Every switch bounce will be hard shorting the cap and creating really noisy fast edges that cause parasitic ringing that can go up over the pin threshold and defeat the purpose of having it. Just do software debouncing, or add a series resistor with the cap and usually an external pull up so you can calculate the time constant

[Matt Thompson @fuzziphy]

@PoseidonROV Yeah, it’s nice when you have access to the top side like right angle 2.54mm pin strips. I usually try and avoid vias at all cost, but a few here and there is no big deal. This board has a lot more than usual

[Matt Thompson @fuzziphy]

@zackslab Thanks brother. It’s hard to get a perfect joint on these little pins with no mask.. dabs of paste flux, copper braid for excess and IPA

[Matt Thompson @fuzziphy]

Yeah, and that’s really the trade off.. $10k in equipment can buy a lot of boards from JLC. Personally it’s more about the ability to experiment and iterate quickly rather than the economics (especially today when all the good parts are SMD and you can’t just perfboard or etch). I wouldn’t really recommend it for any other practical reason.

[Matt Thompson @fuzziphy]

For most things below moderate complexity LOE isn’t much different if you’re populating the board yourself. For something simple I can go from CAD to working PCB inside of an hour.

The CNC I use has a Z probe to mesh compensate the clad, and a 6 tool ATC, so it’s mostly hands off other than flipping and registration pins. Then I use a voltera to print paste directly from gerber, and built in hot plate to reflow.

A lot of boards need very few vias, sometimes just a couple ground stitches. Using as much surface mount as possible is easier. This particular board breaks out 2 PCIe x4 connectors with a SMD ribbon connector and an array of Schottky clamps on the other side, so there’s a lot more vias than I’d typically have.