show me your home lab!
“What’s your choice for a single best aid to an interesting and productive circuit design career? A PhD? An IQ of 250? A CAD workstation? Getting a paper into the Solid State Circuit Conference? Befriending the boss? I suppose all of these are of some value, but none even comes close to something else. In fact, their combined benefit isn’t even worth a fraction of something else. This something else even has potential economic rewards. What is this wondrous thing that outshines all the other candidates? It is, simply, a laboratory in your home. The enormous productivity advantage provided by a home lab is unmatched by anything I am familiar with. As for economic benefits, no stock tip, no real estate deal, no raise, no nothing can match the long-term investment yield a home lab can produce. The laboratory is, after all, an investment in yourself. It is an almost unfair advantage.
The magic of a home lab is that it effectively creates time. Over the last 20 years I estimate that about 90% of my work output has occurred in a home lab. The ability to grab a few hours here and there combined with occasional marathon 5-20 hours sessions produces a huge accumulated time benefit. Perhaps more importantly, the time generated is highly leveraged. An hour in the lab at home is worth a day at work.
A lot of work time is spent on unplanned and parasitic activities. Phone calls, interruptions, meetings, and just plain gossiping eat up obscene amounts of time. While these events may ultimately contribute towards good circuits, they do so in a very oblique way. Worse yet, they rob psychological momentum, breaking up design time into chunks instead of allowing continuous periods of concentration. When I’m at work I do my job. When I’m at home in the lab is where the boss and stockholders get what they paid for. It sounds absurd, but I have sat in meetings praying for 6 o’clock to come so I can go home and get to work. The uninterrupted time in a home lab permits persistence, one of the most powerful tools a designer has.
I favor long, uninterrupted lab sessions of at least 5 to 10 hours, but family time won’t always allow for this. However, I can almost always get in two to four hours per day. Few things can match the convenience and efficiency of getting an idea while washing the dishes or putting my son to sleep and being able to breadboard it now. The easy and instant availability of lab time makes even small amounts of time practical. Because no one else uses your lab, everything is undisturbed and just as you left it after the last session. Nothing is missing or broken, and all test equipment is familiar. You can get right to work.”
- Jim Williams “The Art and Science of Analog Circuit Design”
@wangqq1981 yeah it already did it all, it's done and ready to order lol. i haven't had time to sit down and thoroughly review it yet though, gonna do that this weekend
wow it fixed the unrouted nets, clearance issues, and silk screen while i was gone all day... BUT IT IS STILL LESS POWER DENSE THAN MY HUMAN DESIGNED/ROUTED BOARD, I STILL HAVE AN EDGE!
the real question though is if this will work.
going to review it more in depth when i have time but component placement looks relatively correct and very human like.
okay, used @diodeinc with fable5.2 on a similar spec to the @i2cjak design challenge boost converter board...
it's not totally there yet but i think AI is solving PCB design in the next 1-2 years. i may end up eating my words, didn't think it would happen this soon.
laying out a custom, high(ish)-current boost converter is a much different game than the hobbyist esp32/rp2040 stuff people have been posting.
the design choices it made are remarkably similar to the boost converter i thoughtfully designed over the course of weeks. it's fused, has uvlo/ovlo/ocp, prevents backfeed, deadtime logic. granted, these were all in my spec i provided it.
the diodeinc/fable5.2 board isn't complete, it got stuck and couldn't finish routing 53 nets and has 39 clearance violations. i'm going to see if i can prompt it out of these. it's only $417 worth of fable5.2 credits in. which is strange because i did this test on opus5.5 was more expensive and a much worse result.
i'm still going through schematic and layout, but was pretty wild to see this when i woke up this morning.
[read about what’s happening with AI]
ME: Wow we’re actually legit fucked this is so bad.
[go outside]
ME: Wait those people are all acting like nothing unusual is happening. Maybe I was just in a paranoid bubble? Yeah it must be that. Phew.
[read more about what’s happening with AI]
ME: Wait no we ARE fucked. Shit. It’s all those people outside who are in a delusional bubble.
[go outside]
ME: Wait...
@CapacitAnas@raulizahi@MagnusCarlsen yeah if anything i think a single person or small group of people commanding AI could 100-1000x their output.
probably the best time right now to not be stuck in a dinosaur company with lots of bureaucracy/legacy decisions.
computers have always threatened to contest human abilities.
the profession of "calculator" is non existent today.
the first iphone can beat/tie @MagnusCarlsen in chess 100% of the time.
AI can decimate the best human NL holdem poker players in HU play until they're broke, even if they bankroll manage well.
it can write better code than 99.99% of human software engineers.
the models are now actually getting good at designing hardware.
it is only getting better from here. the future is about to get really interesting.
i still think materializing things in the real world will be the long tail.
having something in CAD is great, but you still need to build it, know how debug, test it, put it in environmental chambers, take it through compliance testing, bodge/fix mistakes... etc.
it's just the digital work that gets eaten, and honestly still requires a fair amount of expertise to prompt/massage something that is correct design wise and manufacturable.
humans will be the meat puppet actuators until humanoids are actually on line.
this is what it reported after it clanked for a few hours:
DRC: no shorts, but 39 clearance findings against the 0.2 mm board rule: 26 are inside footprints (LTC7000A pads, the pre-routed TPSM33606 module) and 13 are MCU fan-out tracks at 0.14–0.19 mm from a via. An early fab-rule check (before signal routing) also flagged the 21 vias inside the TPSM33606 module for a 0.1 mm annular ring against a 0.115 mm minimum; these are unchanged.
Decision for you
The routing is stuck because the placement is too dense for 0.2 mm rules on 2 oz copper. Three ways forward:
Grow the board to about 100 × 62 mm (my recommendation): costs about 10 % power density, keeps 2 oz copper, and gives room to loosen the driver cluster and redo the MCU fan-out cleanly.
Switch outer copper to 1 oz: allows 0.15 mm rules and removes the footprint clearance findings, at roughly 0.5 W more copper loss at full load.
Keep size and copper: I re-place the output-switch driver cluster and rebuild the MCU fan-out by hand; slowest, and it may still end up tight.
i just told it to grow the board to keep the 2oz copper on outer layers.
okay, used @diodeinc with fable5.2 on a similar spec to the @i2cjak design challenge boost converter board...
it's not totally there yet but i think AI is solving PCB design in the next 1-2 years. i may end up eating my words, didn't think it would happen this soon.
laying out a custom, high(ish)-current boost converter is a much different game than the hobbyist esp32/rp2040 stuff people have been posting.
the design choices it made are remarkably similar to the boost converter i thoughtfully designed over the course of weeks. it's fused, has uvlo/ovlo/ocp, prevents backfeed, deadtime logic. granted, these were all in my spec i provided it.
the diodeinc/fable5.2 board isn't complete, it got stuck and couldn't finish routing 53 nets and has 39 clearance violations. i'm going to see if i can prompt it out of these. it's only $417 worth of fable5.2 credits in. which is strange because i did this test on opus5.5 was more expensive and a much worse result.
i'm still going through schematic and layout, but was pretty wild to see this when i woke up this morning.
hey remember that time @i2cjak challenged me to an electronic design challenge and then he PROMPTLY pivoted to SW'e'?
i MERCIFULLY gave him 7 months to catch up… but this board is getting ordered this weekend.