Guy Eschemann

FPGA wizard at @PLC2GmbH, software developer, dad and guitar rookie. Natural health enthusiast. Creator of Opinions are my own.

[Dr Sarah Myhill @MyhillNews]

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[Guy Eschemann @geschema]

@tessfalor @DebBallance @AmandaE53371734 @remissionbiome What is baby aspirin?

[Guy Eschemann @geschema]

@agy_lena True. No one is safe.

[Whitney Dafoe @DafoeWhitney]

I want to have gone into my doctor’s office at my college 19 years ago, when I felt like I had a fever..

See a specialist, get diagnosed with some condition and have them give me a bunch of those marvelous shiny color brochures…

New post on my blog:

https://t.co/exmHqTG29W

[Guy Eschemann @geschema]

The latest version of @Sigasi Studio can warn you about forgotten reset values in clocked VHDL processes. Such a useful feature!
https://t.co/JyljIaoQUd

[Guy Eschemann @geschema]

The people over at https://t.co/UKAI45oGFf asked me a few questions about #FPGA design. You can read the full interview here: https://t.co/AZCJcw3DO6

[Guy Eschemann @geschema]

We're delighted to provide the McMaster Interdisciplinary Satellite Team (MIST) at McMaster University in Canada with free https://t.co/D4fXgVljFs subscriptions to support the development of their nanosatellites!

https://t.co/dX0m5oQ4ox
https://t.co/veJL52rIun

[Guy Eschemann @geschema]

@ATaylorFPGA Now I know why mine cannot be delivered... you bought them all!

[Guy Eschemann @geschema]

Xilinx recommends to keep the number of unique control sets below 7.5 % of total slices to avoid impacting timing and placement. In Vivado, you can query the number unique control sets in your design using the "report_control_sets -verbose" command.

[Guy Eschemann @geschema]

A sometimes overlooked metric in Xilinx #FPGA designs is the number of unique control sets—a control set being defined as the combination of a clock, a clock-enable and a reset signal. Too many control sets prevent the efficient packing of logic into slices.

[Guy Eschemann @geschema]

@Sigasi 85% dark chocolate haha

[Guy Eschemann @geschema]

As a last resort, use out-of-context synthesis to compile the troublemakers with special options. (4/4)

[Guy Eschemann @geschema]

Optimize your RTL code down to an acceptable number of logic levels, based on the rule of the thumb above. (3/4)

[Guy Eschemann @geschema]

Use rules of the thumb, such as 500 ps per logic level, to estimate whether your design has a chance to work at the target clock frequency. (2/4)

[Guy Eschemann @geschema]

When it comes to #FPGA timing closure, it's a good idea to keep an eye on the number of logic levels in your design. In Xilinx (oops, AMD) Vivado you can do this using:

report_design_analysis -logic_level_distribution -extend

Do it post synthesis to save time! (1/4)

[Guy Eschemann @geschema]

A public service reminder to always keep your #FPGA logic under reset while its clock-generating circuit (PLL or MMCM) is not locked. This is especially important for stateful logic like FSMs.

[Guy Eschemann @geschema]

@zipcpu Something like this?
Source: https://t.co/1xF739v8wQ

[Guy Eschemann @geschema]

A good teacher makes me feel like I can fly; a bad teacher gives me the feeling that I'm not smart enough.

[Guy Eschemann @geschema]

@zipcpu And so does quality. When a client comes up with a made up number like that, I ask if he would accept the roof on his house to be only 95% waterproof ;-)