Top Tweets for #GTKWave

over 3 years ago

#fpgafriday time for new #yosys #oss-cad-suite-build #iverilog #verilator #openfpgaloader #gtkwave.....https://t.co/zTOozc09Lt 💥💥💥💯💯❤️💯💥❤️❤️❤️❤️❤️❤️❤️💯💥💥💯💥💥💥💥❤️❤️💯❤️❤️💯❤️❤️💯❤️😕

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almost 4 years ago

Without EDA the logic designer would be a loser! Bless the EDA developers and researchers! #fpga #asic #verilog #vhdl #yosys #xilinx #altera #lattice #gowin #anlogic #simulation #logicDesign #gates #and #or #nand #nor #inv #dff #comb #gtkwave #iverilog #vivado #synopsys #mentor

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almost 4 years ago

Which verilog simulator is your choice? #vivado #iverilog #gtkwave #modelsim #verilator #verilog #logic #design #fpga #asic

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Zip CPU

@zipcpu

over 4 years ago

A special thanks and shout-out to the #GTKWave maintainers for fixing this issue! If you struggle with this, you might wish to build GTKWave from github. https://t.co/qwgOos22gt

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over 4 years ago

#doomchip 'on-ice' version, closer look at the SPIflash QPI texture access for terrain rendering. The raycaster accesses alternatively the heightmap and colormap. Everything has to be precisely orchestrated. Here, using #GTKwave to view signals simulated with #icarusverilog.

sylefeb's tweet photo. #doomchip 'on-ice' version, closer look at the SPIflash QPI texture access for terrain rendering. The raycaster accesses alternatively the heightmap and colormap. Everything has to be precisely orchestrated. Here, using #GTKwave to view signals simulated with #icarusverilog. https://t.co/p70Y7otely

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over 5 years ago

Implemented #i2c #master from scratch on #ice40 #fpga. PoC is #ds3231 #rtc. 400k/bit #fastmode transfer. Displaying hours, minutes and seconds via #8bit #leds #bcd encoded. I like #2wire #protocol. Thanx to #icefun, #yosys, #iverilog, #nextpnr and #gtkwave #opensource 💪

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Le Dahu @realCWolpert

over 5 years ago

Simulation of SPI Master sending last 256 byte from ice40 BRAM to SPI/USB bridge. #Yosys, #iverilog and #GTKWave on #Linux - free and open source, made by awesome people. My friends were sceptical but I like the toolchain a lot (haven't really tried icecube and modelsim, no need)

realCWolpert's tweet photo. Simulation of SPI Master sending last 256 byte from ice40 BRAM to SPI/USB bridge. #Yosys, #iverilog and #GTKWave on #Linux - free and open source, made by awesome people. My friends were sceptical but I like the toolchain a lot (haven't really tried icecube and modelsim, no need) https://t.co/SUO9oZx6bF

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about 6 years ago

Time to call it a night, a last look at my screen. So much fun! (improving the Doom-chip, testing new column buffering approach in simulation with #icarusverilog + #gtkwave, #yosys running in the background, Silice code on the right).

sylefeb's tweet photo. Time to call it a night, a last look at my screen. So much fun! (improving the Doom-chip, testing new column buffering approach in simulation with #icarusverilog + #gtkwave, #yosys running in the background, Silice code on the right). https://t.co/G9gSyIkFZr

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about 6 years ago

Link to scripts and pre-built binaries! 620MB of Open Source treasures for #fpga hardware design under Windows using #MSYS2/#MinGW. Contains #yosys, #nextpnr, #icestorm, #icarusverilog, #gtkwave, #verilator, #riscv toolchain, and compile scripts. https://t.co/eRzyvrMVtP

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about 6 years ago

I want everyone to have #fpga fun, so I am preparing a binary package with all OSS tools for Windows: #yosys, #nextpnr, #icarusverilog, #verilator #gtkwave. Latest addition, the entire #riscv toolchain. All compiled with #MSYS2/#MinGW ! https://t.co/hRo7Nyya8d

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