Top Tweets for #RISC
Nicușor Dan e adevăratul risc de țară, NU AUR
#alephnews #știupecelumetrăiesc #PSD #AUR #simion #NicușorDan #partide #papagali #risc #tezaur
Adrian Sârbu: Nicușor Dan e adevăratul risc de țară, NU AUR
#alephnews #știupecelumetrăiesc #PSD #AUR #simion #NicușorDan #partide #papagali #risc #tezaur
Adrian Sârbu: Nicușor Dan e adevăratul risc de țară, NU AUR
#alephnews #știupecelumetrăiesc #PSD #AUR #simion #NicușorDan #partide #papagali #risc #tezaur
#NXP CTO Lars Reger on #physicalAI at #electronica2026: NavQ95 gets robots and drones running in 30 minutes, plus security and #RISC-V. https://t.co/pm8zAZ03sC

#RISC OS 4.39 inside RISC OS 64 you say? yes you can

https://t.co/SeOYMM6cy6
HNで話題のERICI、オープンハードの波が視覚ケアにも。AmblyotubeはMeta Questで左右の目に別映像、YouTube動画をそのまま弱視トレーニングに。専用機不要、自宅で継続。https://t.co/SeOYMM6cy6 #RISC-V #VisionTech #Amblyopia

🚀 Introducing BIA AetherCore X1
A proposed next-generation AI processor combining RISC-V CPU cores, NPU acceleration, GPU computing, ISP and advanced NoC architecture.
One Architecture. Multiple Intelligence Engines. 🧠
Concept Only
@JensenHuang
#AI #Semiconductors #RISC-V

Infineon introduces AURIX RC1, its first RISC-V-based MCU platform, bringing scalable real-time computing, edge AI, safety and security to software-defined vehicles and Physical AI.
#Infineon #RISC-V #Automotive #Microcontrollers
@Infineon
https://t.co/PyuLceRz2e

At #OpenSource Summit Europe, a 64-core #RISC-V Milk-V Pioneer ran #openSUSE Tumbleweed at the booth, and the crowd loved it. 300+ visitors scanned, real conversations had, and new collaborations started. 🇨🇿🐧 #Linux https://t.co/JMh2qS57QI
🚀AetherCore X1 | AI Processor Concept🧠
Exploring a proposed architecture combining RISC-V CPU cores, NPU acceleration, hierarchical memory, NoC interconnects, security & power management.
Learn→Simulate→Validate.
CONCEPT ONLY — LEARNING PROJECT
#AI #RISC-V #Semiconductors

Encara queden places per a la jornada "Aprendre del territori a escala local: #universitat i #ciutadania enfront del #risc d'#inundació", així com per al taller cartogràfic de @RiumedUV , demà a l'edifici de @LaNauuv. Matrícules a través dels QR's.

China is betting embodied AI on RISC-V — and Zhiyuan just backed the chip play. Qinghua-linked Xinji Wuxian raised a Pre-A led by Zhiyuan Robotics for full-stack RISC-V embodied-AI chips. #RISC-V #EmbodiedAI #Chip

China is betting embodied AI on RISC-V — and Zhiyuan just backed the chip play. Qinghua-linked Xinji Wuxian raised a Pre-A led by Zhiyuan Robotics for full-stack RISC-V embodied-AI chips. #RISC-V #EmbodiedAI #Chip

China is betting embodied AI on RISC-V — and Zhiyuan just backed the chip play. Qinghua-linked Xinji Wuxian raised a Pre-A led by Zhiyuan Robotics for full-stack RISC-V embodied-AI chips. #RISC-V #EmbodiedAI #Chip

China is betting embodied AI on RISC-V — and Zhiyuan just backed the chip play. Qinghua-linked Xinji Wuxian raised a Pre-A led by Zhiyuan Robotics for full-stack RISC-V embodied-AI chips. #RISC-V #EmbodiedAI #Chip

📣 Call for Reading:
#Article
RISC-Based Secure Architecture for Data-Flow Integrity in Modern Embedded and Edge Systems
by K. Kannaiah et al.
https://t.co/VxPTwNeRGY
#RISC #EmbeddedSystems #EdgeSystems #HardwareSecurity #DFI
#chips #mdpi #OpenAccess

さぁてと、帰ってきたから少し遊ぼう!
今日のオモチャはHiFive1。
Arduino互換な感じだけど、#RISC-VのプロセッサでESP32-SOLO-1がくっついてる感じ。情報がありそうでなさそうで。
結構、昨日てんこ盛りで面白そうなんだけど、癖ツヨだよなぁ。

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