it's so funny asking the AI to assess instruction set architectures. I think I bamboozled it with words and conned it into giving me a good assessment.
document has an abstract now. it tells the reader:
- what the architecture is,
- what principle drives it,
- what problems it is trying to solve,
- why they should care.
I think they set my AI to cheerleader mode.
https://t.co/tuZSj8gMTk
I asked Claude about GLYPH's normative naming conventions, which it had overlooked in its default assessment. they also improve the Flesch-Kincaid readability score compared to other ISAs, so I regard it as "accessibility". this is an excerpt from its assessment.
added support to GLYPH for memory type attributes and made various other refinements. the spec is not complete, hence the low score for depth/coverage.
@NOTimothyLottes I recently read an advisory about a cross architecture behavioral difference between whether segment base is set via the GDT, via a special MSR or via instruction. it seems descriptor coherency can vary between implementations. but I donβt have the precise details. sounds bad.
might issue 0.7-release and move to 0.8-current.
Claude says for 0.8, the natural targets would be:
- 32-bit and 64-bit instruction listings
- scalar-max and vector calling conventions
- worked example or reference program
- possibly a glossary
"Each novel element is achieved by a small, clean insight rather than a large engineering effort. That's extremely rare in ISA design, where the usual tendency is to solve problems by adding instructions, registers, or modes."
"Novelty and simplicity usually trade off against each other β novel ideas tend to require new mechanism, which adds complexity. GLYPH manages to be novel by removing mechanism rather than adding it."
it needs bandwidth sensitive compute and memory scheduling. spatial scheduling. tile based GPU schedulers do this but current OS schedulers are not up to the task. itβs not because they couldnβt. itβs because they focused on POSIX and VMS system interfaces from the 1970s.
coherent caches on commodity compute are not efficient for parallel computation and produce lots of cache ping pong. they are efficient for adhoc concurrency like web services. for parallel compute one often wants non temporal access to globally distributed node local memory.