Michael Brennan

[Michael Brennan @meamonb]

Cherryvale is a RISC-V core/SoC i'm working on this summer to learn about fpga and digtal design

Written in Chisel HDL, extensively tested in sim and on a Digilent Basys3 board.

Link: https://t.co/HFmGZnPvM7

[Michael Brennan @meamonb]

One thing that may be a hurdle in the future is the pipeline has relatively low IPC - with 0 cache latency we're at about .45IPC, most of that lost seems to be stemming from branch mispredictions

Curious though to see if we can get a better Fmax than in the past though

[Michael Brennan @meamonb]

FPGA LIFETIME

HOOORAHHHHHHHHHHHH

[Michael Brennan @meamonb]

in the future (for float and multiply units), I can easily swap the current cache implementation out for whatever mem access I need

Feeling very good! Wanna go back to writing more SoC components, big next milestone is gonna be being able to flash from laptop.

[Michael Brennan @meamonb]

Code for the new core is here: https://t.co/GkxiuVOT6t

Tbh I'm really happy with how this has turned out - the RTL is super clean, the stages have specs written for them to check their ready/valid interfaces (thanks Claude!), we'll be able to easily support multi-cycle execute

[Michael Brennan @meamonb]

FPGA SUMMER DAY ????

With CherryTrunk now in place I've been busy rewriting the original RISCV core to support synchronous read memory

Been a bit of a slog but I now have proper interfaces for future I-cache and D-cache, we can talk to bus, and support multi-cycle mem access

[Michael Brennan @meamonb]

halt and reset the core

[Michael Brennan @meamonb]

FPGA SUMMER DAY 26

RAHHHHHHH

Uart debug master -> cherrytrunk bus crossbar -> basys IO slave peripheral

We can now control the board over UART!!!!

Serial client written in rust btw

[Michael Brennan @meamonb]

I think for the core I'll keep instructions and data as separate memory spaces, so I don't have to worry about caching yet or having every mem access take multiple bus cycles

Need to also add jalr support, cleanup the execute stage, add some basic control registers so we can

[Michael Brennan @meamonb]

@splinedrive What do you for sim/verification? Plain unit testing, UVM, ?

[Michael Brennan @meamonb]

FPGA SUMMER DAY 25

Was looking to post a demo tn but I've been sniped into rolling my own UVM-style testing library for chisel

[Michael Brennan @meamonb]

Dispatcher has been written (and tested)!! https://t.co/aF4YT2Rsx0

This will take bytes off of UART, convert them into mem read/writes, then send reads back over UART

Work on bus interconnect and really putting everything together starts tmrw

[Michael Brennan @meamonb]

Wanna write up some FV for the RX module - after that, write the encoder/decoder so we can send/receive bus messages, then start putting it together with the basysIO module I built last week

[Michael Brennan @meamonb]

Taking things a lot slower and simulating every step has been huge - first just the UART TX, then TX + FIFO, and now this all together

S/o to @zipcpu as well tutorials have been a huge help!

[Michael Brennan @meamonb]

FPGA SUMMER DAY 23

Big progress - UART passthrough going through custom uart RX, uart TX, and fifo module!!!!

[Michael Brennan @meamonb]

Wanna write up some FV for the RX module - after that, write the encoder/decoder so we can send/receive bus messages, then start putting it together with the basysIO module I built last week

[Michael Brennan @meamonb]

@yishan Would love to see something like this commercialized but that does say 8kV in the video????