In the newly released v2.2.4 of the Ripes @risc_v simulator, you'll find a @mattgodbolt-inspired C-to-assembly runtime overlay of the instructions (and source lines) present in each processor pipeline stage!
https://t.co/BEV3SuPAjh
@notCamelCase @yannsionneau Just swinging by here to say that I've been playing around with integrating "real" processors into Ripes, through Verilator. Initial experiments have been done with a PicoRV32 model, and things work great! https://t.co/rQomW0sT1T