Erik Rigtorp

[Erik Rigtorp @rigtorp]

@pkhuong https://t.co/tZOJV4RpVB but it's C++ and not plain C

[Erik Rigtorp @rigtorp]

@trav_downs @lemire If the optimizer where supplied value ranges it could perform a numerical analysis to determine if any overflow can occur. Many programs operate correctly because inputs are reasonably constrained. Maybe we can have the cake and eat it too?

[Erik Rigtorp @rigtorp]

@pkhuong You should ask Pelle Evensen: https://t.co/uEUPDYMJ1I

[Erik Rigtorp @rigtorp]

@mekarpeles Wildfires are most likely primarily influenced by other factors: https://t.co/MK5Qjl0GvB

[Erik Rigtorp @rigtorp]

@penberg @fleming_matt @pshufb Yes

[Erik Rigtorp @rigtorp]

@glcst @penberg For example I use https://t.co/lBFbZNuCtY and it would benefit from having SCHED_BATCH threads for disk IO and bulk network IO, while keeping UI and some parts of networking as SCHED_OTHER.

[Erik Rigtorp @rigtorp]

@glcst @penberg Thread-per-core is great when you can dedicate a machine or subset of cores to an application. When needing to share cores the thread-per-core architecture gives less information to the scheduler. Any work on quantifying the trade-offs?

[Erik Rigtorp @rigtorp]

@glcst @penberg Yes, but if someone writes a desktop app in Go for example. The app wouldn't be able to prioritize interactive processing and bulk processing. In C++ I could create SCHED_BATCH threads for bulk processing and SCHED_FIFO for example audio processing.

[Erik Rigtorp @rigtorp]

@penberg @fleming_matt Sure it's just not a very interesting paper IMHO. In particular it misses a discussion on flow steering. See @pshufb article https://t.co/LICaDUK3mp. Industry is definitely ahead of academia here.

[Erik Rigtorp @rigtorp]

@penberg @fleming_matt That paper misses all the non-obvious sources of latency. Looking at just virtual memory there is lots of sources of latency: https://t.co/S5p3eFpfuj

[Erik Rigtorp @rigtorp]

@phoronix Can confirm that ROCm 3.7 works on Navi. https://t.co/NpkPCto2jH

[Erik Rigtorp @rigtorp]

@AMD #ROCm version 3.7 finally supports Navi 10! I've tested it on my 5700XT card. Hopefully @PyTorch will run on Navi 10 now. Steps to reproduce on @fedora: https://t.co/PJ42oj9jTc

[Erik Rigtorp @rigtorp]

On the latest CPU microarchitectures (Skylake and Zen 2) AVX/AVX2 128b/256b aligned loads and stores are atomic. I wrote a small program isatomic that I used to verify this. https://t.co/b5jZtnBmCR #AVX #SIMD #x86

[Erik Rigtorp @rigtorp]

@trav_downs @bitcharmer @mjpt777 @majek04 It also makes it worthwhile to remove PAUSE from all your concurrency primitives in latency critical code when running with SMT disabled.

[Erik Rigtorp @rigtorp]

@tvaneerd @__simt__ @MarekKnapek @a_williams @jfbastien @blelbach I wanted to check what happens. Looks like you don't want to do this because codegen will be bad on clang currently.

[Erik Rigtorp @rigtorp]

@tvaneerd @__simt__ @MarekKnapek @a_williams @jfbastien @blelbach Now to derive the theoretical semantics from the standard wording was an interesting exercise. Does this mean that a store release must effectively always be a store acquire-release?

[Erik Rigtorp @rigtorp]

@tvaneerd @__simt__ @MarekKnapek @a_williams @jfbastien @blelbach Right, I've only reasoned from how could acq and rel be implemented most easily on x86, ARM, PowerPC and basically acquire must be a compiler barrier and release a full memory barrier.

[Erik Rigtorp @rigtorp]

@tvaneerd @__simt__ @MarekKnapek @a_williams @jfbastien @blelbach With the definition of synchronizes doesn't this become undefined behavior?
int f() { lock(); int x = y++; unlock(); return x; }
int z = f() + f();
Since f() + f() is unsequenced, the release sequence is undefined.

[Erik Rigtorp @rigtorp]

@tvaneerd @__simt__ @MarekKnapek @a_williams @jfbastien @blelbach Even if the standard has a exception for std::mutex it's now possible to implement mutex using std::atomic::exchange() and std::atomic::wait()/notify(). It seems that all properties of mutex should come from that theoretical implementation in order to be consistent.