RISC-V.chip.haus

News and information about the RISC-V instruction set architecture and its implementations, brought to you by @ChipHaus.

[linuxdevices @linuxdevices]

SiFive RISC-V Rack Cluster and custom PC power up with HiFive Unmatched: SiFive and AB Open demoed a “SiFive RISC-V Rack Cluster” that runs Linux on four of SiFive’s RISC-V U74 based HiFive Unmatched boards. AB Open and Future Computing recently announce… https://t.co/VaidWiKsXf

[The Register @TheRegister]

Chatter around GPUs for RISC-V is growing https://t.co/n4eEATB7UM

[RISC-V.chip.haus @RISCVchip]

“RISC-V Business: Testing Gaming and More on the HiFive Unmatched from @SiFive” (@Level1Techs, 14 min.)
📺 https://t.co/jtpwcmN88w

[Mouser @MouserElec]

Register for a LIVE panel discussion with @MicrochipTech and @crowd_supply exploring the future of RISC-V this Tuesday!

Details: https://t.co/ZxNBkNiFrL
#webinar #RISCV #IoT #5G

[Lup Yuen Lee 李立源 @MisterTechBlog]

#Mynewt #RISCV is Hardcoded for SiFive FE310 ... Here's our fix for #PineCone #BL602 @ThePine64

https://t.co/VszmThGxyg

[Masayuki@FPGA開発日記 @dev_msyksphinz]

"Hardware description language Chisel & Diplomacy Deeper Dive" my presentation video in RISC-V Study meetup online Dec.18 is uploaded! #RISCV

https://t.co/ZuhrQmkKTz

[OGAWA, Tadashi @ogawa_tter]

=>
"MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect", @LucaBeniniZhFe , to appear at DATE21 (arXiv, Dec 5, 2020) https://t.co/sqoSDhy2Po
@pulp_platform
256 fast RV32IMA (#RISCV) “Snitch” cores
Shared L1 scratchpad memory pool, 5cycles
700MHz
GF 22FDX

[OGAWA, Tadashi @ogawa_tter]

@LucaBeniniZhFe @pulp_platform =>
"A Tiny #RISCV Floating-Point Unit", L. Bertaccini, ETH Zurich, RISC-V Summt 2020, Dec 8
PDF https://t.co/SZapKWujPu
@pulp_platform
Integer Snitch core is optimized for area
Fast to Tiny-FPU
Trading area for latency
Snitch, arXiv, Oct 8 https://t.co/ZyUPFrrx9Q
@LucaBeniniZhFe

[OGAWA, Tadashi @ogawa_tter]

=>
"MEEP's emulated accelerator architecture", Nov 15, 2020 https://t.co/KFV3Ij2910
VAS Accelerator Tile
Shared L2: 4 MB
Core
#RISCV
Vector Processing Unit via OVI
Systolic Arrays
"The Future HPC will be open", Prof. M. Valero, Keynote, IEEE HPCC 2020 https://t.co/7ftfBhAmiw

[RISC-V.chip.haus @RISCVchip]

Project Oberon 2013 on RISC-V
🛠 https://t.co/8zUwRQxRAv
💬 https://t.co/uscGbjwWzG

Cf. https://t.co/TrzTZvyNKg

[OGAWA, Tadashi @ogawa_tter]

=>
RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture, RISC-V Global Forum, Spe 3, 2020
09:58 https://t.co/U7X5ZYpsBF
https://t.co/v8LL2eahYE
developed by Imagination
Sep 2 https://t.co/5jKLgNvwW9
A-Series GPU https://t.co/999BX3eyK8
Firmware processor

[RISC-V.chip.haus @RISCVchip]

“What is a system-on-chip (SoC), and why do we care if they are open source?” (@BunnieStudios, 2020-11-10)
👉 https://t.co/6slqMFWWGJ
💬 https://t.co/m3J6XQdKMj
💬 https://t.co/3JwmFqoT4O

[Hackster.io @Hacksterio]

.@SipeedIO plans $12.50 Linux-capable RISC-V dev board family based on the XuanTie C906: https://t.co/QcOTa9495x

[PULP Platform @pulp_platform]

As the #RISC-V summit is approaching, this week we would like to introduce PULP's speakers. On Tuesday, 8 December 2020 at 11:00 am we will have Luca Bertaccini presenting "A Tiny RISC-V Floating-Point Unit" https://t.co/nugzPHfIQX

[AB Open @ABOpenLtd]

A Look at the RISC-V PC from SiFive.

https://t.co/fmVM5lONgy

#RISCV #FOSSi

[TechCrunch @TechCrunch]

SiFive’s new PC is bringing open-source computing closer to reality https://t.co/PesK3bDOD6 by @dannycrichton

[RISC-V.chip.haus @RISCVchip]

“A Plan 9 C Compiler for RISC-V RV32GC and RV64GC” (Richard Miller, 2020-10-19, 33 min.)
📺 https://t.co/bAjlM12rtI

[RISC-V.chip.haus @RISCVchip]

Basic Computer Design: A Simple RV32I CPU (John’s Basement)
📺 Part 2 https://t.co/j9rlbrjZ2o
📺 Part 3 https://t.co/TImtbaYZ6n

[RISC-V.chip.haus @RISCVchip]

“SiFive/RISC-V Questions with James Prior” (@Level1Techs, 52 min.)
📺 https://t.co/OdbtvP1JFz