The Chip Engineer

if it runs on silicon, i'm probably talking about it.

[The Chip Engineer @thechipengineer]

@Abhi16619 @Boeing_In @Boeing Yeah sure

[The Chip Engineer @thechipengineer]

✈️ Excited to share that I’ve joined @Boeing_In as an Electronic Design Apprentice!

Grateful for everyone who supported me throughout this journey. 🙏

A new chapter begins, and I’m looking forward to learning, growing, and making the most of this opportunity.
@Boeing
#Boeing

[The Chip Engineer @thechipengineer]

HBM is hitting a physical wall.

At Hot Chips 2026, SK hynix put a hard number on it:
HBM stacks are capped at 775 microns - the same thickness as a standard 300 mm logic wafer.

That ceiling is now shaping the next generation of AI silicon.

What that forces:
• Taller stacks (12-Hi → 16-Hi) leave almost no room left
• Hybrid bonding becomes mandatory for HBM5
• Packaging - not just DRAM bits - is the new bottleneck
• Micron also warned the “HBM wafer penalty” vs DDR5 is getting worse every generation

Same week: Intel EMIB is showing up as a real CoWoS alternative (SK hynix, Google, MediaTek), because giant silicon interposers are expensive, yield-risky, and capacity-constrained.

The lesson for chip designers:
You can keep adding cores.
You cannot keep stacking memory the same way.

The next fight in AI hardware is vertical - bonding, thickness, power delivery, and how you attach HBM without killing the package.

❤️ Like | 🔁 Repost if you’re watching the packaging race

#ArchitectureExplained #HBM #HBM5 #HotChips #AdvancedPackaging #ChipDesign #Semiconductor #3DIC #Memory

[The Chip Engineer @thechipengineer]

@Synopsys just validated the world’s first 3D-stacked PCIe 6.0 PHY at full 64 GT/s.
They took an existing 5 nm 2D PCIe 6.0 test chip, split it, added through-silicon vias (TSVs), and re-signed it against 3D process design kits.

Result:
• Face-to-face stacked dies
• 64 GT/s per lane (PAM4)
• Up to 128 GB/s on an x8 link
• Receiver eyes clearing the PCIe 6.0 BER spec by multiple orders of magnitude

Why this matters:
In traditional packaging the PHY sits at the edge of the die and routes straight to the substrate.
In face-to-face 3D stacking the bottom die is flipped - so signals must climb to upper metals, reverse direction, and drop through TSVs.
That forces new keep-out zones, tighter electromigration rules, and careful signal-integrity trade-offs.

This is more than a PHY demo.
It proves high-speed I/O can live inside a true 3D stack - exactly what next-gen AI accelerators, HPC chiplets, and multi-die systems need.
The multi-die era just got a working high-speed highway.

#3DIC #PCIe6 #AdvancedPackaging #ChipDesign #Semiconductor #Synopsys

[The Chip Engineer @thechipengineer]

@intel 18A-P just landed its first major external customer: Socionext.

The Japanese custom SoC specialist is using Intel’s performance-enhanced 18A-P node for next-gen high-performance compute chiplets aimed at AI, HPC, and data-center workloads.

Key points:
• 18A-P builds on RibbonFET GAA + PowerVia backside power
• Delivers up to 9% higher performance or 18% lower power vs base 18A
• Full design-rule compatibility → easier IP reuse
• First product: a high-performance compute chiplet

This is Intel Foundry proving it can win real external design wins on a leading-edge node while TSMC still dominates most advanced work.
Process innovation + chiplet architecture = more options for custom silicon.

What do you think - will more ASIC houses multi-source between TSMC and Intel in 2027–28?

#ChipDesign #VLSI #Semiconductor #18A #Chiplet #ASIC #intel #TSMC

[The Chip Engineer @thechipengineer]

HPE is Hiring -ASIC Design Engineer!

Role: ASIC Design Engineer
Location: Bengaluru
Join Hewlett Packard Enterprise and work on next-generation high-performance Networking ASICs.

What you’ll do:
• Define & architect high-performance hardware blocks
• Micro-architecture development & RTL design (Verilog)
• Collaborate with Verification & Physical Design teams
• Timing closure, power optimization & debugging

Requirements:
• https://t.co/4UptWjS338 / https://t.co/HoPdtknG2U in Electrical / Electronics Engineering
• Strong Verilog RTL coding & digital logic design skills
• Experience in ASIC design methodologies
• Knowledge of multi-clock domain, CDC, memory subsystems is a plus

Great opportunity to work on advanced networking silicon at HPE!

Apply here:
https://t.co/xWpNBu1CRM

Tag hardware engineers who should apply 👇
Share & spread the word!

#HPE #ASIC #RTLDesign #VLSI #Networking #BengaluruJobs #HardwareEngineering

[The Chip Engineer @thechipengineer]

Key takeaway:
Pipelining overlaps instructions.
Out-of-Order Execution finds useful work.
Register Renaming removes false dependencies.
Superscalar execution lets multiple ready instructions run in parallel.
That’s how modern CPUs turn one instruction stream into massive parallel activity.

❤️ Like | 🔁 Repost if this helped.

Next: Architecture Explained #014 — SIMD: How CPUs Process Many Numbers With One Instruction.

#ArchitectureExplained #ComputerArchitecture #Semiconductor

[The Chip Engineer @thechipengineer]

Architecture Explained #013
Superscalar Execution: How CPUs Execute Multiple Instructions at Once

A CPU pipeline can keep multiple instructions in progress.
But here’s the next problem:
Why process only one instruction per clock cycle? If several instructions are independent… why not execute them together?

That’s exactly what superscalar execution enables.

#ArchitectureExplained #ComputerArchitecture #CPU

[The Chip Engineer @thechipengineer]

Here’s the important limitation:
A 6-wide CPU doesn’t automatically execute 6 instructions every cycle.
Dependencies, branches, cache misses, and available units all limit real throughput.
Superscalar design creates the opportunity for parallelism.

#CPU #Performance #Microarchitecture

[The Chip Engineer @thechipengineer]

Architectural registers are the names your program sees.
Physical registers are the hardware the CPU actually uses.
Register Renaming bridges the two - eliminating false dependencies and enabling more parallel execution.

❤️ Like | 🔁 Repost if this helped.

Next: Architecture Explained #013 - Superscalar Execution: How CPUs Execute Multiple Instructions at Once.

#ArchitectureExplained #ComputerArchitecture #Semiconductor

[The Chip Engineer @thechipengineer]

Architecture Explained #012
Register Renaming: How CPUs Eliminate False Dependencies

Imagine two employees named Alex.
Your manager says:
“Alex, finish this report.”
Which Alex?
The problem isn’t the work.
It’s the name.
Modern CPUs face a surprisingly similar problem with registers.

#ArchitectureExplained #ComputerArchitecture #CPU

[The Chip Engineer @thechipengineer]

Without Register Renaming, modern Out-of-Order CPUs would spend far more time waiting.

It’s one of the key technologies that unlocks the performance of today’s processors.

#CPU #ChipDesign #Engineering

[The Chip Engineer @thechipengineer]

To your program, nothing changes.
It still thinks it’s using R1.
Behind the scenes, the processor keeps track of dozens - or even hundreds - of physical registers.

#Microarchitecture #ComputerArchitecture #CPU