Tiny Tapeout

Tiny Tapeout makes it easier and cheaper than ever to get your designs manufactured on a real chip!

[Tiny Tapeout @tinytapeout]

@GregDavill Nice photo! It's cool to be able to see through the epoxy. Any ideas on how to get the epoxy more clear? gentle polishing?

[YosysHQ @YosysHQ]

$1200 too much for a Vivado license?

How about:

$0 - Yosys
$0 - nextpnr
$0 - OpenROAD
$30 -Subnautica 2
$30 - Blahaj
$180 - Glasgow interface explorer from @crowd_supply
$950 -160kum^2 of Sky130 silicon + ASIC from @tinytapeout

#opensource #FPGA #ASIC

[logic destroyer @splinedrive]

What makes me most proud is that something like this probably never existed before under these constraints. Maybe being a bit crazy made it possible.

A Linux capable RISC V SoC with an Sv32 MMU implemented as a real ASIC on @tinytapeout (8×4 tiles) using the IHP Leibniz Institute for High Performance Microelectronics PDK, capable of running xv6, µLinux (noMMU), and booting mainline Linux including Linux 7.0.

External BootROM over a shared SPI bus also used for an SD card, Ethernet controller with IPv4 and IPv6, and other SPI devices. Runs from external PSRAM in full clock mode with two 512 line caches for instructions and data plus TLBs. Performance roughly comparable to Unix workstations from the late 80s and early 90s.

The chip was built in a 130 nm process on 1.7 mm × 0.7 mm of silicon with more than two meters of wiring. CPU core and SoC were designed completely from scratch. ASIC integration was done independently during one vacation week based on my own design.

I work professionally as an embedded/Linux developer and have pursued logic design as a hobby for about five years. Some ASICs even got taped out.
Thanks to @UriShaked for help with ASIC integration, Leo Moser for advice on ASIC-related questions, and @matthewvenn for making this possible through TinyTapeout.

[Tiny Tapeout @tinytapeout]

Last weekend saw another world first for Tiny Tapeout - custom silicon conference swag!

At @hackaday in beautiful Lecco, we gave out 160 of these lovely chip on board business cards. Each one features a https://t.co/Awtx7bcIvB die, wire bonded onto a PCB.

[Matthew Venn @matthewvenn]

5 years ago my first ever chip had a deadly error. This is the video I couldn’t make then - join me at 18:00 CEST for the premiere!

https://t.co/PUMzld8nYp

[BreakingTaps @BreakingTaps]

I had a sneak peak at this video, it's very cool!

FIB is such a cool technique to allow editing of live chips

[Greg @GregDavill]

Fresh and custom silicon day! 😍

This is a multicore riscv soc design based on @OlofKindgren's serv processor core.

Based on GF180MCU PDK, and fabricated through https://t.co/dfBOQSs5ZD 🚀

[Matthew Venn @matthewvenn]

Corner is the #ASIC terminology of the week!
https://t.co/c7VhQ6Ummf

In the last month, Corner has been the 5th most popular out of 42 terms.

[Tiny Tapeout @tinytapeout]

30 more PCBs released on TTSKY26b, and tapeout extended by 1 week to 18th May.

[Tiny Tapeout @tinytapeout]

@lazybanananann working on it!

[Tiny Tapeout @tinytapeout]

@ckdur cool! looks nice on VGA playground too: https://t.co/T6arhdd9FL

[Tiny Tapeout @tinytapeout]

Want to get your hands on a real lithography photomask? How about some silicon wafers?

Enter our demoscene competition for a chance to win one!

https://t.co/9A2keuJ72t

Last 6 days to get involved!

[Matthew Venn @matthewvenn]

We cut a microscopic wire inside a chip with an ion beam, then brought it back to life with platinum gas!

My latest video is a collaboration with @Zeptobars, and I’m releasing it as a Youtube premiere at 18:00 CEST on Tuesday 12th May.

https://t.co/PUMzld8nYp

[Tiny Tapeout @tinytapeout]

Want to get your hands on a real lithography photomask? How about some silicon wafers?

Enter our demoscene competition for a chance to win one!

https://t.co/9A2keuJ72t

Last 6 days to get involved!

[Tiny Tapeout @tinytapeout]

We have 17 entrants so far to the #ASIC #demoscene competition! Don't miss your chance to win some excellent prizes.

Details and sign up here: https://t.co/9A2keuJ72t

[NitHub Unilag @nithub_lag]

Over the past few weeks, the @nithub_lag × @IEEEorg Silicon @tinytapeout Bootcamp has been on the move.

Participants moved from basic concepts to actually working through digital chip design using open-source tools.

Tomorrow, the Demo Day holds.

Looking forward to it.

[Tiny Tapeout @tinytapeout]

400 responses so far! Help us get another 200 and you could win a cool silicon wafer!

[Tiny Tapeout @tinytapeout]

To help guide us over the next year, we’d really appreciate 2 minutes of your time to fill out this short survey:

https://t.co/XmN0Fkiqc1

As a thank-you, one lucky respondent will win a genuine 150mm silicon wafer.

[Tiny Tapeout @tinytapeout]

We have 17 entrants so far to the #ASIC #demoscene competition! Don't miss your chance to win some excellent prizes.

Details and sign up here: https://t.co/9A2keuJ72t

[ieee_atbu_student_branch @ATBU_IEEE_Sb]

We are hosting a workshop on chip/ic design tomorrow. Courtesy of IEEE Division 1, we could have our designs taped out🤗. Can't wait to see how it goes. Shout out to @tinytapeout and the IEEE societies and Councils within Division 1

[Tiny Tapeout @tinytapeout]

To help guide us over the next year, we’d really appreciate 2 minutes of your time to fill out this short survey:

https://t.co/XmN0Fkiqc1

As a thank-you, one lucky respondent will win a genuine 150mm silicon wafer.