Vimal Manivannan

Verification Engineer #semicon-professional.

[Chad Wallace @siliconcodesign]

You can have the most powerful AI accelerator in the world, but it's meaningless if it can't move data efficiently.

The question is, why is data movement so expensive, and how do chip architects design around it?

I wrote a first-principles primer that explores these questions, covering MAC operations, SRAM vs DRAM, model & accelerator performance metrics, and "Eyeriss", a classic AI accelerator that ties these concepts together.

https://t.co/YFkl71U9yT

[Chad Wallace @siliconcodesign]

Everyone talks about HBM as the key bottleneck of AI compute, but most explanations only cover one piece of the system.

What's missing is a holistic understanding of how all the pieces fit together.

HBM isn't just a single domain problem, but a complex system-level co-design challenge involving thermals, mixed signal circuits, signal integrity, and packaging.

I wrote an all-in-one technical overview that connects these disciplines and explains the major engineering challenges involved. This article covers:
- A History of HBM
- Major alternatives to HBM
- How DRAM works
- How the base die transmits signals in "wide and slow"
- Key features in the base die to correct for signal nonidealities
- Thermal gradients in the stackup
- Reliability challenges from stacking multiple layers
- Custom HBM

https://t.co/9U2KCr9Ga4

[OGAWA, Tadashi @ogawa_tter]

"Power Processors & IBM i: A Brief History of the Past 25 Years", W Starke, Power Processor Chief Architect, IBM, CEC 2026, 26-06-16 https://t.co/oAurL6cHjr
POWER4 (2001)
…
Power11 (2025)

<= Power Processor Roadmap: Power11, Mem Arch, .., W Starke, 06-15 https://t.co/F8qWHLxF4W

[灰狐 @huihoo]

Open-source VLSI design lectures and practical exercises developed by the Integrated Systems Laboratory at ETH Zurich.
https://t.co/ZHbhPfTN5v

The curriculum leans heavily on an open-source EDA tool ecosystem. Utilizing a fully open-source EDA design flow in conjunction with IHP's open-source PDK.
https://t.co/mm3Nv0GlZG

[Swaroop Kumar Yadav @S2SmeX]

Open sourced VLSI course for free.
https://t.co/yRLfQLkgOp

[Denis Laskov 🇮🇱 @it4sec]

Military drones and ways they communicate: UAV relays and mesh networks (in theory and in the news) 📡🛩️၊၊||၊🛩️👨🏻‍💻

More details on:
LinkedIn: https://t.co/XFiwQsJcgt
Substack: https://t.co/5DMBG4Z5CI
Telegram: https://t.co/NmwW1XWgdV

[OGAWA, Tadashi @ogawa_tter]

@miyox @yyasuda @ebiken @O_FiberLady
NVIDIA Principal HW System Architectによる CPOについての講演ビデオ/スライドです (26-10-08) https://t.co/NePjI6zose
前半は HPC Interconnect系で後半は CPOの軌跡から今後。講演者は 2025年迄 IBMで MOTION (ARPA-E)/P775 (俗称 "畳") に関わった方です。

[PULP Platform @pulp_platform]

The slides from Luca's talk "Energy efficiency and Power management for AI accelerators - Tackling the MW rack challenge" presented at the "Sustainable Computing Architecture: From Silicon to Datacenter" workshop in Athens are available online: https://t.co/BaagK1TM1g

[AADITYANSHA @aadityansha_06]

A small video to Understand Computer architecture especially Low-Level with in-depth intuition Behind CPU, Cache, memory hierarchy and locality and refresh overhead.
The video went quite long otherwise would have covered more advance topics
https://t.co/XnpJi9k0z3

[Math Cafe @Riazi_Cafe_en]

ETH Zürich's "Mathematical Foundations for Finance"

PDF: https://t.co/ol5GbP3qj6

[灰狐 @huihoo]

并行超低功耗（Parallel Ultra Low Power，PULP）
PULP Platform @pulp_platform
PULP as a parallel ultra-low power platform
PULP as an open-source platform
https://t.co/hVOppwVqNg

PULP 始于 2013 年，由苏黎世联邦理工学院（ETH Zürich）的集成系统实验室（Integrated Systems Laboratory, IIS）与博洛尼亚大学（University of Bologna）的节能嵌入式系统（Energy-efficient Embedded Systems, EEES）研究组共同发起
旨在利用 RISC-V 开放指令集架构（ISA）及开源协作式硬件设计，探索并开发新型高效计算架构
PULP 最初聚焦于低功耗设备，现已扩展至大型高性能系统领域，涵盖了多核 RISC-V 小芯片（chiplets）等应用

经过十余年的发展，PULP 项目已成功流片了 50 多款芯片
已发布了基于开源 RISC-V 指令集架构的高效 32 位和 64 位实现
涵盖了从简单的微控制器到各类外设及完整系统
其中，最先进的 OpenPULP 版本为低功耗多核 IoT 处理器树立了新的标杆
此外，PULP 还支持多种 API ，例如 OpenMP、OpenCL 和 OpenVX
从而助力实现应用程序的灵活移植、开发、性能调优及调试

另外 PULP 平台 zero-riscy 内核（ibex）是 OpenTitan 的安全控制核心
https://t.co/DfvCQw4qC6
OpenTitan 由 Google、lowRISC 等联合推动，是全球首个开源硅基可信根（RoT, Root of Trust）参考设计，侧重于高安全等级、可量产落地的硬件安全芯片
https://t.co/D6YCBEkPQX

[PULP Platform @pulp_platform]

Check out now Tim's completed doctoral thesis "Scalable Interconnects for Integrated Accelerators" in the ETH Zurich Research Collection. See https://t.co/JhWw1B3P9N @fischetim

[Math Cafe @Riazi_Cafe_en]

MIT's "Computer Systems Security" (6.858) by Nickolai Zeldovich

Covers buffer overflow exploits, web security, side-channel attacks & more.

Lecture notes and videos: https://t.co/e9bbJg7lOK

[Math Cafe @Riazi_Cafe_en]

UC Berkeley's "Modern Computer Vision"

Lecture Videos: https://t.co/6edGcb3bYf

[灰狐 @huihoo]

非常值得关注的 FPGA CPU 博客
https://t.co/n1xGU9RNWo
之前长期沉寂的 FPGA CPU News 也可一并关注

作者 Jan Gray 于 2003 年离开微软后致力于硬件架构、FPGA 和 RISC-V 开放指令集架构的研究，并创立了 Gray Research LLC
https://t.co/rE0tlcrVqk
Gray Research LLC is a Silver Founding Member of the RISC-V Foundation.

此前他在微软工作期间曾是 .NET CLR 性能团队的核心成员，并在 2003 年 6 月发表了广为人知的经典技术长文《Writing Faster Managed Code: Know What Things Cost》
https://t.co/rNHAkOKKz6

[Sandeep Srinivasa @sandeepssrin]

Emudhra digital certificates have been compromised.

Best of luck filing your GST, ROC ...or any income tax filings that need DSC.

I think the govt needs to put out a TV advisory. You need to upgrade your browsers and root stores all across India.

https://t.co/pN5mNIwnYH

[The Rocket Media @TheRocketMediaX]

India built its own GPS. Now it's building the chips to make it work!

For years, India has had its own satellite navigation system, NavIC, developed by ISRO.

But there was a catch.

While Indian satellites could transmit navigation signals from space, the tiny chips needed to receive those signals were largely imported.

A team at IIT Bombay decided to change that.

After nearly six years of research, their work has evolved into DhruvaPro, an indigenous navigation chip developed by MumbaiSemi, an IIT Bombay spinout.

It can receive signals from India's NavIC alongside GPS, Galileo and BeiDou.

And the science behind this tiny chip is fascinating!

[Denis Laskov 🇮🇱 @it4sec]

Hacking on-ship navigation and how to trace an attacker: An intro to NMEA 2000 for security researchers. 🚢🧭👾💉👨🏻‍💻

More details on:
LinkedIn: https://t.co/PFu6uADvWG
Substack: https://t.co/XzROlAGTmw
Telegram: https://t.co/87nG4fMGMa

[The Rocket Media @TheRocketMediaX]

Quantum Computer using Particles of Light!

Yes, you read it right.

Bengaluru-based Quanfluence has raised $10 million to develop a full-stack photonic quantum computer.

And its approach is fascinating.

Many leading quantum computers rely on superconducting circuits that must be cooled to temperatures close to absolute zero.

Quanfluence is pursuing a different architecture.

Its processors use photons, the particles that make up light, to encode and manipulate quantum information through optical circuits.

The company plans to integrate indigenously designed photonic chips, electronics and software into a working system.

With early processors targeted for 2027, India could soon have another homegrown contender in the global quantum computing race.

[PULP Platform @pulp_platform]

You can now find Yichao's PhD thesis " Toward Thousand-Core Shared Memory: Scalable Many-Core Architectures for Data-Intensive Workloads" in the Research Collection of ETH Zurich: https://t.co/J7eMXujDGx @yichao_zh