Modern DRAM is based on a brilliant design from IBM.
But, we're still paying for a latency penalty that's existed since the 60s!
In this video, I'm introducing my research project (Tailslayer) that immensely reduces p99.99 latency on traditional RAM!
By implementing a hedged read strategy taking advantage of (undocumented!) channel scrambling offsets, I've gotten as much as 15x reductions in tail latency.
The technique works across Intel, AMD, Graviton, DDR4, DDR5, x86, ARM, you name it.
Check out the C++ lib I wrote, watch the video, and try it yourself!
Ever wondered what speculative execution looks like cycle-by-cycle? I just added cycle-level uarch introspection to my CPU research kernel. Here's a graph showing speculative loads occurring (that never retire as they are after a faulting instruction).
unauth, unassoc remote code exec on the Marvell Avanstar Wifi chip SoC used in Playstations, Xbox, Surfaces, Chromebooks, Samsung phones and more in under five minutes attack time. Bonus second stage escalation in the linux drivers, PoC on steamlink.
https://t.co/s54QBc5mDK
New article! Japanese cars are more interesting when you can fully exploit them... Digging into an old ECU, old protocol, speed limiter, and some other things: https://t.co/alyydYTaAL
I've just put down part of what I was teaching about pointers, the article hasn't been reviewed (it's github you can do issues or even PR if you want).
I've tried to be as correct as possible, but with C, who knows ...
https://t.co/LDRlbsIS6f
The planning for the #LSEWEEK is out ! Join us @EPITA for this singular event !
Le planning de la #LSEWEEK est sorti ! On vous attend @EPITA ce weekend !
New lightning talks on the 12th of June in amphi 4 @EPITA! Planning is available: https://t.co/i47HGmMqOh
Les LTs du 12 Juin arrivent !
Rendez vous en amphi 4 :)
Le planning est disponible sur https://t.co/i47HGmMqOh