This is a HBM4E wafer from Computex (photo koreajoongangdaily)
Die is 1c 32Gb, minimum 140mm2 size. Likely 145-150, since HBM4 JEDEC package size is 155.6mm2. HBM eats fab cap as die size goes up every gen. There is no memory supply coming pre-2030 that offsets this.
Vera talk is heating up, so resharing these from GTC: NVIDIA's Vera CPU 8-way compute tray up close.
Liquid-cooled, SOCAMM LPDDR5X packed around the CPUs, with 1.2 TB/s memory bandwidth and 1.8 TB/s NVLink-C2C on the spec board.
Now the servers are getting close to landing. HPE brought the ProLiant DL394 Gen12 to COMPUTEX, and Dell is bringing its own Vera systems to market.
#NVIDIA #Vera #HPE #Dell @NVIDIAAI
Intel intros Diamond Rapids "Xeon 7" CPUs built on 18A-P: packing up to 192 cores, 16-channel memory, PCIe Gen6 support, launching in 2027. https://t.co/jm6G3BIg9W
BREAKING NEWS: Jensen just announced WINDOWS on NVIDIA ARM consumer PC. Unlike Apple transition to ARM M1 with Rosetta 2 transpiler, we are not convinced that Windows on NVIDIA ARM will work well.
intel is more like AMD on it's Xeon 6 + clearwater forest:
12 x compute tile intel 18A
3 x active base tile: intel 3
2 x IO tile: intel 7
12 x EMIB tile: EMIB 2.5D
4 x DDR5 memory base tile
intel Xeon 6:
3 x compute tile:
2 x io tile:
EMIB tiles
the tiles number is more than 400% increased.
this is really interesting.
chiplet designs are going to everywhere: except the NVIDIA GPU.
you can't have the high performance and low power consumption at the same time. this is commond sense, there is no magic in compute.
ARM VS X86
as INTEL and AMD's chiplet designs:
huge cores / ~ > 2 times users can be servered than one VERA CPU.
this is simple math. ARM won't take all. even 50% is diffcult in server CPU market.
NVIDIA VERA: 88
Intel Xeon 6+: 288
Intel Xeon 6: 288
AMD Turing:192
AMD Venice: 256