Antmicro

Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.

[Zephyr Project @ZephyrIoT]

Zephyr RTOS has reached space again! Read how @antmicro and @AetheroSpace are using Zephyr-controlled companion MCUs in NxN and NxA space computers built around NVIDIA Jetson Orin and Thor edge AI platforms.
https://t.co/MY6HcELHFj

[Antmicro @antmicro]

In collaboration with @ADI_News, we improved @Arm v8.1-M support in @renodeio with M-Profile Vector Extension (a.k.a. Helium), extending Renode's use cases even further with DSP and ML applications. See how you can use Renode for testing Cortex-M platforms:
https://t.co/F2YvG4sbuL

[Antmicro @antmicro]

Antmicro supports the @NVIDIA Jetson ecosystem with accelerated end-to-end product development building around its Yocto-enabled open source hardware and frameworks for OTA (RDFM), factory testing (Protoplaster), AI (Kenning) and more. Read our #NVIDIAGTC Taipei at #COMPUTEX Press Release: https://t.co/yPz0zo53KI @NVIDIARobotics @yoctoproject @linuxfoundation

[Antmicro @antmicro]

Watch our 2nd talk from @FossiFoundation's Latch-Up 2026 discussing the @CHIPSAlliance vision to align efforts towards faster and more collaborative design and testing of silicon with the newly restructured SV Tools and Veer projects: https://t.co/29wZiK6Cqm @risc_v

[Antmicro @antmicro]

Introducing the Zephyr Sensor Anomalies library for embedded devices running @ZephyrIoT. Learn how our lightweight tools can help you train and evaluate AI anomaly detection models when paired with Kenning: https://t.co/PTaEYh1Okm @linuxfoundation

[Antmicro @antmicro]

Watch our talk from @FossiFoundation's LatchUp 2026 in Waterloo, Canada discussing the latest developments in UVM compliance for Verilator and our effort towards 4-state logic support: https://t.co/DKaVtsSrHR @CHIPSAlliance @linuxfoundation

[Antmicro @antmicro]

We improved force/release statement support in Verilator to be compliant with the IEEE SystemVerilog standard. Read about our implementation and other related developments: https://t.co/QBatedtdBR @CHIPSAlliance @linuxfoundation

[Antmicro @antmicro]

We introduced a new resynthesis strategy in the @OpenROAD_EDA ASIC design toolchain, based on a genetic algorithm. See how this approach can help you optimize your design and how it complements the existing simulated annealing strategy we developed previously: https://t.co/18lBRUgYTO @Google

[Antmicro @antmicro]

With @renodeio support for the @RISC_V @Andes_Tech D25F core, platforms like the Egis ET171 can be simulated easier. Find out how we expanded the fingerprint module test suite for @Google's @ZephyrIoT-based Chromebook EC and how Renode aids in CI-driven testing of production-grade devices: https://t.co/ZsqQa6mIS9

[Antmicro @antmicro]

Our new open hardware SDI-Fiber Adapter enables reliable, high-quality video transmission over long distances in challenging, high-EMI environments. Learn more about the design and our customization and integration services: https://t.co/fNinVR1Btl

[Antmicro @antmicro]

We're on track towards the next big milestone for Verilator: read about our proposal for initial support for four-state logic, and join us at @FossiFoundation's Latch-Up 2026 in Canada this weekend to learn more:
https://t.co/JPbDh7v0Yn @CHIPSAlliance @linuxfoundation

[Antmicro @antmicro]

Antmicro's open hardware baseboard for @NVIDIA Jetson Orin available to buy directly on System Designer!

Max flexibility in small footprint to kickstart your next edge AI device: supports Orin Nano/NX, customizable, multiple power sources & interfaces, compatible with our OSHW video accessories.

Use our services to take your project from PoC to a customized, future-proof product ready for deployment at scale: OTA with RDFM, AI benchmarking and deployment with Kenning, factory testing with Protoplaster, and more.

Now also available with fast, direct shipping in Europe: https://t.co/jTPvOlIcOD

[Antmicro @antmicro]

Read about the recent improvements to our DC-SCM reference platform and other related developments, and meet us at the @CHIPSAlliance booth at @OpenComputePrj #OCPBarcelona26 to learn more about our data center-oriented tools and workflows: https://t.co/BzNRSjvjTp @latticesemi @NXP

[Antmicro @antmicro]

Join us at @FossiFoundation Latch-Up 2026 to learn about our recent contributions to the Verilator project, including improved verification, UVM support, and the next major milestone, four-state logic support:
https://t.co/Std3VkEDpj @CHIPSAlliance @linuxfoundation

[Antmicro @antmicro]

In our first talk at @FossiFoundation Latch-Up 2026 we'll walk you through the activities and objectives of the recently restructured @CHIPSAlliance SV Tools Project, and discuss tools such as Verible, RISC-V DV and SV-tests:
https://t.co/mCf2sjvZPX @linuxfoundation @risc_v

[Antmicro @antmicro]

We expanded our open source thermal simulation flow with a Computational Fluid Dynamics-based methodology for steady-state simulation of conjugate heat transfer in complex designs. See how we tested this approach on an @NVIDIA Jetson AGX Thor setup:
https://t.co/vjapGZJd4U

[Antmicro @antmicro]

The @CHIPSAlliance @risc_v VeeR EL2 core includes an optional Dual-core Lockstep mechanism for applications such as side-channel mitigation & rad-hardening. See how DCLS can enhance your safety-critical aerospace, automotive and industrial control systems: https://t.co/J8e1H0mF18

[Antmicro @antmicro]

Happy to be sponsoring @FossiFoundation Latch-Up 2026! Get up to speed with Verilator's latest verification capabilities, UVM, assertion support, and the next big step: 4-state logic, and learn about the new @CHIPSAlliance SV Tools Project https://t.co/tJ6Bi5wIk2 @linuxfoundation

[Antmicro @antmicro]

Meet us at @OpenComputePrj's OCP EMEA Summit. Bridging the breadth of @CHIPSAlliance projects, we'll showcase Guineveer, an extensible @RISC_V reference design based on VeeR EL2 and Topwrap, and the open source lint/debug/verification capabilities enabled by the new SV Tools Project https://t.co/2iUVDKNZv2