Future Intelligence Lab

We build next-gen intelligence

[Future Intelligence Lab @FiLabsHQ]

@nvidia @LGE_Global @JensenHuang Nice

[Future Intelligence Lab @FiLabsHQ]

@JinweiT50522 Design & viz!

[Jinwei Tang @JinweiT50522]

Why isn't every EDA company making satisfiying visualization tools for engineers? @FiLabsHQ

[Future Intelligence Lab @FiLabsHQ]

@Nuo_Xu1 “When tool time dominates, agent design becomes a scheduling problem: what to cache, what to run incrementally, and what to do while waiting.”

[Nuo Xu @Nuo_Xu1]

Step-level routing is the right unit. In hardware workflows the steps are not interchangeable: RTL generation, waveform reasoning, and PPA report reading stress different capabilities.

The open question is the routing signal: task type, or feedback from the tool that just ran.

[Nuo Xu @Nuo_Xu1]

Most hardware agent results are reported on private setups, which makes them hard to compare.

A recent benchmark uses 2,787 designs and 90 questions that require locating evidence across source files, logs, netlists, and reports.

Shared task sets turn demos into progress.

[Future Intelligence Lab @FiLabsHQ]

Busiest booth and coolest demo! Last day at DAC26! #chip

[Future Intelligence Lab @FiLabsHQ]

Busiest booth and coolest demo! Last day at DAC26! #chip

[Future Intelligence Lab @FiLabsHQ]

FiLabs is getting crowded at DAC26 Booth 729 #DAC26 #ChipDesign

[Future Intelligence Lab @FiLabsHQ]

Future Intelligence Labs is exhibiting at #DAC2026 in Long Beach!

📍 Booth 729, Long Beach Convention Center
🗓 July 27–28, 10:00 AM–6:00 PM
🗓 July 29, 10:00 AM–4:00 PM

Stop by and meet the team.

#EDA #ChipDesign #Semiconductor #AgenticAI

[Future Intelligence Lab @FiLabsHQ]

Future Intelligence Labs is exhibiting at #DAC2026 in Long Beach!

📍 Booth 729, Long Beach Convention Center
🗓 July 27–28, 10:00 AM–6:00 PM
🗓 July 29, 10:00 AM–4:00 PM

Stop by and meet the team.

#EDA #ChipDesign #Semiconductor #AgenticAI

[xm @xianruimeng]

saying eda is cooked over Kimi K3 is missing the fine print.

What’s real: an agent ran the full RTL→PnR→verification loop end-to-end in 48 hours. Long-horizon agentic chip design is here. That’s bigger than the skeptics admit.

What’s not: open-source EDA, Nangate 45nm — an academic library. Simulation only. No production PDK, no DRC sign-off, no foundry. Zero silicon risk taken.

That’s a great demo. (@FiLabsHQ did this a year ago using openroad). It’s not a tape-out.

The real challenge isn’t RTL that closes timing in sim. It’s carrying a design through verification, physical closure, and sign-off on a production PDK — and owning the outcome.

EDA didn’t die this week. But the gap between “AI demo” and “AI-delivered silicon” is exactly where the next generation of design houses gets built.

[Future Intelligence Lab @FiLabsHQ]

@MehreenNMalik @GaryMarcus This is exactly why model-chip co-design is the endgame. Hosting frontier models on generic silicon is a margin race to zero. Silicon designed for the model — and the model tuned for the silicon — is where the real cost and latency advantage lives.

[Future Intelligence Lab @FiLabsHQ]

https://t.co/yoj5MOPZkN
AI / semis

[Nuo Xu @Nuo_Xu1]

A dataset built only from final RTL misses how the design was actually developed.

Failed tests, rejected edits, and review decisions explain why the code changed—not only what the final version looks like.

That process data may be especially valuable for training models.

[Future Intelligence Lab @FiLabsHQ]

from workload to design to fab all in us … interesting!

[Jukan @jukan05]

WSJ: Apple secured an exemption from semiconductor tariffs in exchange for committing to use Intel’s fabs.

WSJ: Apple will manufacture not only Mac chips but also iPhone chips at Intel.

$AAPL $INTC

[NVIDIA @nvidia]

Enterprises don’t just need agents that perform. They need agents they can shape, govern and improve as their business evolves.

That’s the idea behind our work with LangChain.

Read more: https://t.co/3hu5eARj5N

[Future Intelligence Lab @FiLabsHQ]

As we move into the inference phase, it’s always about hardware and software co-design. Glad to see our team member’s work on this! Way to go!

[WinsonChen @winsonchen108]

Excited to be presenting our work on Stitch CUDA at #ICML2026! 🎉

If you’re attending, I’d love to chat about LLMs for GPU programming, code generation, and software systems. Come stop by our poster!

Poster Session 8 #115
07/09 5:00 - 6:45PM

[Future Intelligence Lab @FiLabsHQ]

@Nuo_Xu1 Yup!

[Nuo Xu @Nuo_Xu1]

Fabs are necessary, but they do not automatically increase design throughput.

As AI workloads push more custom silicon, design productivity becomes part of the bottleneck: architecture exploration, reusable IP, verification capacity, EDA flow automation, and PPA closure.