@azonenberg@d33r4wg @nixie_guy Definitely. I have also very often had boards with highly optimized via stitiching and teardrops performing almost the same as no optimized via-ridden traces.
@azonenberg@d33r4wg @nixie_guy Sweet. Mind if I ask how come those Rs and Cs didnt end up on the bottom layer, and let you route your pair on top? Seems spacey enough at the first glance
@azonenberg@d33r4wg @nixie_guy Oh really? We are dealing with the crazy Stratix boards whose insane power ICs leave no space for outer routing, which would be a really nice cost reduction
@azonenberg@d33r4wg @nixie_guy My team prefers both fill&cap and backdrilling. Backdrilling is a lifesaver if you need to get rid of the via stubs, but cant integrate blind vias into your design,
@azonenberg@d33r4wg @nixie_guy I see, thanks for explanation. I'm also not really happy with how it looks. But i guess it does the job for big pad to via ratio.
@azonenberg@d33r4wg @nixie_guy If I may add, just for completness sake, a backdrilled via, that seem like the seems like a good solution for the OP's problem
@AT89_C51 You re right this time, it's I2S. To clarify it a bit more, there is a one 24MHz master clock, 44.1kHz sample clock and 1.41MHz bit clock, and only one data signal :)
@phyzome @kristofeI@veritasium@Cosmic_Horizons@Lutron The amount of the field that will radiate from the battery to the bulb, untethered from the cables, will be unmeasurably small, let alone enough to light it up.
@phyzome @kristofeI@veritasium@Cosmic_Horizons@Lutron Not only that, but the 99.99%of the field is contstrained within a millimeter away from the cable edge. So the electron movement will "arrive" at the same time when the most of the fields arrive.