Andrew Zonenberg @[email protected]

Infosec, RE, high speed digital, T&M, network hardware, microscopy, FPGA/ASIC, @IOActive, KD2HKV, #SoOthersMayLive. Lead dev of glscopeclient. Tweets are my own

[Andrew Zonenberg @[email protected] @azonenberg]

I've received a lot of questions about my various open source projects, status of them, etc.

Made a public google doc with everything:
https://t.co/WmszAhNZIq

[Andrew Zonenberg @[email protected] @azonenberg]

@BreakingTaps That's the biggest comb drive I've ever seen...

[Andrew Zonenberg @[email protected] @azonenberg]

@Fraser_RG @funranium Yep this was my thought too. Also useful after other kinds of hazmat incident.

[Andrew Zonenberg @[email protected] @azonenberg]

@tom_verbeure @EndoOleg It's very common to abuse FPGA LVDS inputs as comparators.

I made a 100baseTX Ethernet PHY on an FPGA using two LVDS inputs and three resistors as a 1.5 bit 500 Msps flash ADC.

[Andrew Zonenberg @[email protected] @azonenberg]

@Astro_Chuck @RFgeekPC Yeah the large wavelength is annoying.

I've been thinking of building a C-band (5.8 GHz ISM/amateur band, giving me the option of operating under either set of regs) PESA for a while.

Original dream was AESA but those are $$$$$ :(

[Andrew Zonenberg @[email protected] @azonenberg]

@TracketPacer @kwiat_riot_1 @petergjones @EthernetAllianc (also I'm not really active on here except replying when I'm specifically requested, all of my regular posts are on Mastodon now)

[Andrew Zonenberg @[email protected] @azonenberg]

@TracketPacer @kwiat_riot_1 @petergjones @EthernetAllianc Triggering is also problematic unless you can probe TX_EN/RX_EN of one of the endpoint PHYs, because the scrambling means you have continuous toggles even when there's no packets in flight.

Assuming you want to decode vs just seeing an eye pattern for SI work.

[Andrew Zonenberg @[email protected] @azonenberg]

@fluxotronlabs @pepijndevos As long as you don't mind 2-3 WFM/s over SCPI at best, dropping to <1 at deeper memory, sure.

I like scopes that can push Gbps of waveform data to a PC but the list is short.

[Andrew Zonenberg @[email protected] @azonenberg]

@mtaht @networkservice @ioshints The next gen design (LATENTORANGE) is going to use a much larger FPGA with more SERDES lanes (probably Xilinx Kintex UltraScale/Ultrascale+).

LATENTRED is trying to cram 24x 1G baseT + 1-2x 10G SFP+ uplink into an XC7K160T.

[Andrew Zonenberg @[email protected] @azonenberg]

@mtaht @networkservice @ioshints I mean the datapath is all FPGA so you might have to do some tweaking, but if there's enough gates free I don't see why not.

That said, the initial (LATENTRED) switch design is using a fairly small FPGA so I'm not sure how much fanciness you could fit in it.

[Andrew Zonenberg @[email protected] @azonenberg]

@ioshints @networkservice I've mostly moved to Not-Twitter (see username on my profile) and am posting a fair bit about the project over there. Only checking in here every once in a while to point people at what I'm doing there.

Current status: debugging power supply issues causing SGMII BER problems.

[Andrew Zonenberg @[email protected] @azonenberg]

@networkservice @ioshints I can't speak to commercial switch chipsets, but https://t.co/pNn7qbhvjr

[Andrew Zonenberg @[email protected] @azonenberg]

@networkservice @ioshints The MAC address table in my (WIP) open hardware switch manages all learning and lookups in gateware. No CPU interaction is required whatsoever during normal operation; all it does is translate ASCII text CLI commands to register writes when you change VLAN settings etc.

[Andrew Zonenberg @[email protected] @azonenberg]

@Ascii211 But did you reflash drive firmware too and verify with a JTAG/SPI dump? :P

Side note, this is (one of) the reason I run all of my browsers in VMs that I can trivially blow away if there's a problem.

[Andrew Zonenberg @[email protected] @azonenberg]

@TracketPacer Lab rack *of FPGAs*?

[Andrew Zonenberg @[email protected] @azonenberg]

@FizzOtter Most of the folks I interact with have been there largely, or exclusively, for months now. I'm barely on here anymore.

[Andrew Zonenberg @[email protected] @azonenberg]

@tom_verbeure @splinedrive @MoonbaseOtago @samsoniuk @ATaylorFPGA @controlpaths So by using a BUFGCE on the PLL output, this is avoided.

I only do this with clocks that are stably derived (i.e. coming from an oscillator) rather than something from a CDR that is expected to change speed or come/go at run time.

[Andrew Zonenberg @[email protected] @azonenberg]

@tom_verbeure @splinedrive @MoonbaseOtago @samsoniuk @ATaylorFPGA @controlpaths This is important if you only use the FPGA POR to initialize registers and don't have an explicit RTL reset - you need to *never* give the logic a clock pulse that's too short once the POR clears (which happens way before the PLL locks).