SpinalHDL

[SpinalHDL @SpinalHDL]

SpinalHDL webinar the 16 december :
https://t.co/8coYQKkhT2

[SpinalHDL @SpinalHDL]

@iamtommythorn @ferristweetsnow HDL for "Hardware Description Library" of course ^.^
Library in the meaning of being a set of function/utilities in a Scala / Python / Rust and all the other rainbow's colors

[SpinalHDL @SpinalHDL]

@pdp7 @enjoy_digital Ahh likely the template on which that is based suggested uarch to be organisation,cpu_name

[SpinalHDL @SpinalHDL]

@WillFlux @fpga_dave @mad_archer_ @dolu1990 @enjoy_digital It has LRSC + AMO support in the D$ (single CPU system). But this can be disabled to save area. So that's why the emulator layer still contains the atomic emulation as a fallback.
There is also the cacheless config, which only implement LRSC in hardware and need the emulation :)

[SpinalHDL @SpinalHDL]

@jackakattack @OlofKindgren @tom_verbeure @chisel_lang Thanks :)

[SpinalHDL @SpinalHDL]

@jackakattack @OlofKindgren @tom_verbeure @chisel_lang Right, rocket-chip inspired the VexRiscv decoder implementation quite much :)

[SpinalHDL @SpinalHDL]

@dvc94ch @BruceHoult @oe1cxw @symbiotic_eda @marcschettke @bitshiftmask @ico_TC @rustembedded @rustlang @llvmorg VexRiscv RVC done released :)

[SpinalHDL @SpinalHDL]

@Benathon @Neko_Ed *out of sync*

[SpinalHDL @SpinalHDL]

@Benathon @Neko_Ed I recently changed the memory mapping of Briey and Murax,
Maybe you are experiencing issue because the VexRiscv hardware is out of thing from the software memory mapping ? Try to git pull everything again and regenerate things :)

[SpinalHDL @SpinalHDL]

@Benathon @Neko_Ed What do you mean by the stack ? the SP register ?
There is the boot assembly code that should be executed before branching main : (also contain the reset vector)
https://t.co/1Wxe9lWHYM

So a reset only initialize the PC and some CSR

[SpinalHDL @SpinalHDL]

@SamuelAFalvoII Good point, i will document where the inspiration came from. Then while SpinalHDL look very much like Chisel, it isn't a clone, as
- It solve many of the Chisel issues
- It explore many design pattern that Chisel left over
- Its implementation is completley different

[SpinalHDL @SpinalHDL]

@wavedrom I just commited an example where an 32 bits GPIO is directly interfaced with the CSR:
https://t.co/bVdrzvU7yq
Note that the CSR rw is targeting a register. if it target an combinatorial signal, the written value will only remain one cycle

[SpinalHDL @SpinalHDL]

@wavedrom Feature onWrite/onRead/isWriting/isReading on the CsrPlugin added. Just be carefule as the onWrite/onRead block will happen at the very end of the component elaboration ^^ Also check out the CustomCsrDemoPlugin, is is much cleaner now

[SpinalHDL @SpinalHDL]

@wavedrom Ahh then i need to add a bit more API to provide an update event. shouldn't be complicated.

[SpinalHDL @SpinalHDL]

@wavedrom Feature added, see a simple demo which add an instruction counter and a cycle counter into the CSR :
https://t.co/AvHtNa9rRi

[SpinalHDL @SpinalHDL]

@wavedrom Which kind of CSR access do you need ? Read/Write is enough ? Do you need to know when an access is done at a given access (event) ?

[SpinalHDL @SpinalHDL]

@wavedrom @wavedrom Jakob is right :)
So currently there is no clean way to add custom CSR, but it is something that i should add.
I will take a look this evening to see which kind of API i could add :)

[SpinalHDL @SpinalHDL]

@wavedrom @risc_v Now up to 1.40 DMIPS/Mhz at 198 Mhz on Artix 7 : D

[SpinalHDL @SpinalHDL]

New #SpinalHDL documentation : https://t.co/4DYPOOJpxm
Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

[SpinalHDL @SpinalHDL]

@3yakuya Try spinalHDL :)
It's a scala library that allow you to describe your hardware without using this rock age #VHDL !