Papon Charles

[Papon Charles @dolu1990]

@GMahovlic Just got gigabit ethernet support, it eat 766 Mbits/s in RX with iperf3 (in debian) :D

[Papon Charles @dolu1990]

Running Debian with a quad core VexiiRiscv softcore + Litex SoC on a Efinix FPGA at 200 Mhz :
https://t.co/IA98nLuGKA

#riscv #fpga

[Papon Charles @dolu1990]

@fontamsoc (dhrystone with no inline, coremark with many additional compilation flags)
Both number in the previous post are for 32 bits RV32IMA

[Papon Charles @dolu1990]

@fontamsoc For single issue, it is mostly between :
relaxed btb/branch timings (very close to what was used in the orconf talk at 200 Mhz):
- 1.45 Dhrystone/MHz 2.96 Coremark/MHz
stressed btb/branch timings + late alu :
- 1.74 Dhrystone/MHz 3.41 Coremark/MHz

[Papon Charles @dolu1990]

@fontamsoc Overall, to keep the Nax area "small" on FPGA, a few concession have been made :
- Rescheduling the instruction stream require to wait that all the previous instructions commits.

[Papon Charles @dolu1990]

@fontamsoc On Vexii and Nax, both issue handle jump/branch

[Papon Charles @dolu1990]

@fontamsoc Hi,
Hmm not realy for a few reasons :
- Coremark doesn't test the memory system performance (where OoO is great at)
- Coremark contains a big CRC loop which use random branch (Big penality for deep OoO pipelines)
- ...

[Papon Charles @dolu1990]

@ico_TC @curliph Here it is :

[Papon Charles @dolu1990]

#riscv Dual core NaxRiscv running Debian on Artix 7 FPGA :
https://t.co/X49tOEfjx5

[Papon Charles @dolu1990]

@yannsionneau I think the 35T should be ok for single core 32 bits version of Nax + litex SoC, so, shuold be able to run buildroot.

[Papon Charles @dolu1990]

@yannsionneau I only tried on Xilinx 7 so far, reason is their distributed ram are pretty good as far as my understanding goes. Not sure how well it will fit on ECP5, but it should work out the directly. everything is FPGA agnostic (but use a lot of asyncronously readed ram

[Papon Charles @dolu1990]

@yannsionneau Yes, the L2 is very visible XD
The config is :
2xRV64GC 100MHz (slowest Artix 7 speed grade), 16KB I$ 16KB D$ each, 256 KB L2.

[Papon Charles @dolu1990]

@SpinalHDL Recording and powerpoints refered in https://t.co/vQez3GRAbC

[Papon Charles @dolu1990]

@SpinalHDL Starting now on https://t.co/JGC0s6Izg6

[Papon Charles @dolu1990]

@enjoy_digital @BrunoLevy01 @enjoy_digital @BrunoLevy01 Tested on NaxRiscv running debian (RV64GC@100Mhz) : -O2 => RAYSTONES=307.870 <3
With -ffast-math => 390.002

[Papon Charles @dolu1990]

@OlofKindgren @BrunoLevy01 @suarezvictor @samsoniuk @pipelinec_hdl @ultraembedded @sylefeb XD

[Papon Charles @dolu1990]

@minut_e @pftbest @enjoy_digital Yes, likely it is how it works on some other arch.
NaxRiscv implement some custom instruction to flush.

[Papon Charles @dolu1990]

@minut_e @pftbest @enjoy_digital One thing to know, as there is no memory coherency, can't use the litex SD controller, nor the OHCI one, as they use DMA.