ultraembedded

CPU designs, digital HW IP, emulation and embedded system projects

[ultraembedded @ultraembedded]

I think I've built myself an HD (720p50) video player out of an #FPGA, #RISCV, #MJPEG and 27,000 lines of Verilog! Going from 800x600 -> 1280x720 just worked with 10 more MHz! I actually plan to sit down and watch a movie on this one evening! https://t.co/TTG7huzyZW

[ultraembedded @ultraembedded]

@TheRetroHQ No, but I think @wren6991 had a RISCV core with debug/OCD support

[ultraembedded @ultraembedded]

@wren6991 Maybe, one day!

[ultraembedded @ultraembedded]

@wren6991 I treat them as a pipeline flush/fence and hold a global pipeline lock blocking new issue until they complete. Simplifies things a bit, but makes them slower.

[ultraembedded @ultraembedded]

@wren6991 I put another ALU in the LSU just for the AMO ops. It’s quite an annoying extension to implement, esp when mixed with an MMU, precise faults, etc.

[ultraembedded @ultraembedded]

@jonmasters @Arm Unmistakable reminder of a UK 80’s class room there. I seem to remember more ribbon cables being involved though. I owe a lot to my Acorn Electron 😀

[ultraembedded @ultraembedded]

I couldn’t resist - just ordered a zynq 7020 and another ArtyA7 😀

[Digilent @DigilentInc]

Tuesday's #CyberWeek2021 deal is a doozie - we're giving 50% (yes, half off) of ANY Arty board featuring @XilinxInc tech. We call it "The Arty of the Deal".

https://t.co/kGG9Die97r

[ultraembedded @ultraembedded]

@GregDavill Are you doing something with HDMI and USB2 by chance ?!

[ultraembedded @ultraembedded]

@arjenroodselaar @GregDavill @PaulStoffregen Implementing the PCIe link is definitely non-trivial, with the ‘reward’ for all that effort being a single supplier proprietary protocol Ethernet PHY...

[ultraembedded @ultraembedded]

@tom_verbeure @bitsbytesgates I like it, a lot!

[ultraembedded @ultraembedded]

@azonenberg @GregDavill I think I used sigrok when I was doing SD/MMC gateware. But I’d like to try glscopeclient someday.

[ultraembedded @ultraembedded]

@mntmn These printfs look sort of familiar! It’s a ULPI setup isn’t it? If you DM me some more details / source versions used, I might be able to take a look tomorrow night.

[ultraembedded @ultraembedded]

@fontamsoc @enjoy_digital 16KB per way (32KB total). Yeah - I was planning to switch to LiteEth soon.

[ultraembedded @ultraembedded]

Running iperf on Linux on my RV32IMA RISC-V CPU core. 13Mbit/s TCP perf is not impressive. Investigating why. Hmm.. 950K instruction cache refills per second causing the CPU to stall 35% of the time! Need more size/ways/levels, or maybe I could implement compressed ISA extension!

[ultraembedded @ultraembedded]

@mntmn I used the USB host core in another project with a ULPI Phy: https://t.co/D5VAS9bN2w
In case this helps with connectivity issues, etc.

[ultraembedded @ultraembedded]

@mntmn Nice!

[ultraembedded @ultraembedded]

@MoonbaseOtago Yes, and Verilator is indispensable for this kind of stuff for speed reasons. I found snapshots (saved from a c model, restored in RTL sim) really useful to reduce the Linux boot debug time too. I’d be interested to hear about your design flow for something meaty like your CPU.

[ultraembedded @ultraembedded]

@mntmn Nice. What frequency is the CPU running at?

[ultraembedded @ultraembedded]

@splinedrive @sylefeb Nice!