Jim Lewis

VHDL Verification Specialist, OSVVM author, VHDL Trainer, Yogi

[Jim Lewis @SynthWorks]

@PandoraSupport On Windows, the Pandora APP no longer remembers my login credentials. Is Windows still supported?

Support says: "Unfortunately, I am unable to provide any additional information or a timeline as to when you can expect to see this resolved."

Really?

[Jim Lewis @SynthWorks]

@Dell @DellCares I just moved the location of my 3 year old Beautiful 40" Dell Monitor (U4320Q) in my office. Now with day light on it, I can see that has a stress crack. It has never been impacted by anything. Tech support says no to support. Now what?

[Jim Lewis @SynthWorks]

@jeremyyamaguchi @balajis Add to that, use of curse words by people who ordinarily do not curse.

[Jim Lewis @SynthWorks]

Be sure to vote in Aldec's FPGA User Survey 2022 and log your vote for your favorite FPGAs, your favorite FPGA design and verification language (such as VHDL), and your FPGA verification methodology (such as OSVVM)

https://t.co/dlclAkpNw2

#FPGA #VHDL #OSVVM

[FirstEDA Limited @FirstEDA]

Online Advanced VHDL Verification Training Courses - September - https://t.co/H6fm79rPYT

[Guy Eschemann @geschema]

Been working on an SPI to AXI4-Lite bridge recently. A beta version is now available on GitHub: https://t.co/N4jMN7H4VU
Thanks to @SynthWorks and @Sigasi for helping out.

[Jim Lewis @SynthWorks]

Join me on Thursday's webinar to learn about how OSVVM's Advanced VHDL Verification Data Structures simplify their usage.

https://t.co/2rFtNZli29

[Jim Lewis @SynthWorks]

Join me at our upcoming webinar to learn how OSVVM has created simulator independent scripting and best in class test suite and test case reports.

https://t.co/2m0vXVANWJ

#vhdl #verification #osvvm

[Jim Lewis @SynthWorks]

Looking to improve your VHDL testbench capability? #OSVVM is the right solution. OSVVM is developed by leaders in the VHDL standards community and has all the pieces needed for verification.

Webinar series starts on Thursday May 26. See: https://t.co/NEMPjv0zkh

#vhdl #fpga

[Jim Lewis @SynthWorks]

Instructor lead, on-line VHDL classes from VHDL expert and IEEE VHDL Standards WG Chair. Details at: https://t.co/1bJAzeHsb7

With our "half day" on-line format, we do on-line classes right. #vhdl #osvvm #verification

[Jim Lewis @SynthWorks]

It is great to see Aldec's good support of the VHDL-2019 standard. It is nice to see the hard work of the IEEE 1076 Working Group pay off. Having spent 1000's of hours on this effort myself, I am grateful to Aldec for implementing this.

[DesignAndReuse.com @designreuse]

Advancing VHDL's Verification Capabilities with VHDL-2019 Protected Types https://t.co/P2cPt3Hu1m #semiEDA @AldecInc

[Patrick Lehmann @PaebbelsLemmi]

Lately, me and @unaimarcor worked on https://t.co/1HUG3K8h0U to simplify #githubactions for #Python projects. It supports: unit testing (#pytest), code coverage, static type checking (#mypy), packaging, publishing to PyPI, test reports and Sphinx documentation on GH pages.

[Jim Lewis @SynthWorks]

@oe1cxw We can have nice, consistent things - it is called VHDL 😉

[Jim Lewis @SynthWorks]

VHDL+OSVVM 2021.10 Functional Coverage Reports
Now the big difference between #vhdl+OSVVM vs SystemVerilog+UVM functional coverage reporting is the cost. OSVVM is free (#foss) and only requires a basic VHDL-2008 simulation license.

Full article is here: https://t.co/VCig7RcPQ7

[Jim Lewis @SynthWorks]

@don_dingee Texas as opposed to where else? The article implies that it was Taylor Texas vs Austin Texas and Austin lost due to power grid reasons.

[Jim Lewis @SynthWorks]

@NASA @ESA_Tech @JHUAPL @NASA But what if you change its trajectory and it hits the earth?

[Jim Lewis @SynthWorks]

OSVVM 2021.10: Build Summary Reports

When we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed.

Full article is here: https://t.co/POunR99izS

#vhdl #osvvm #verification #foss #opensource

[Jim Lewis @SynthWorks]

OSVVM has created EDA simulation tool independent scripting using a TCL procedure based API layer that abstracts and simplifies running VHDL simulations. Run Aldec, Siemens, Synopsys, GHDL, or Cadence with the same scripts

Article here: https://t.co/NVv4AtySlY

#vhdl #osvvm

[Jim Lewis @SynthWorks]

@Daniel_J_Payne My linked article points out that, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM.

Just looking to do the same thing

[Jim Lewis @SynthWorks]

OSVVM & UVVM: Differences and Unification

Currently OSVVM and UVVM are largely duplicating what each other is doing. This a waste of time and resources.

Lets unify and work together: https://t.co/AnMnJzxXT2

#osvvm #uvvm #vhdl #verification

[Jim Lewis @SynthWorks]

@OlofKindgren @satnam6502 @GroqInc Funny, I had the same thought and added a pirate theme to it.