mshalan

| AI for chip design | Open Source EDA & Hardware | OpenLane | Caravel Chip |DFFRAM | Lighter | CloudV

[MIT CSAIL @MIT_CSAIL]

How long it took 25% of the US to adopt new technology:

⚡ Electricity: 46 years
☎️ Telephone: 35 years
📻 Radio: 31 years
📺 Television: 26 years
🖥️ Personal computers: 16 years
🌐 World Wide Web: 7 years
📲 Smartphones: 4 years
🤖 GenAI: 2 years

v/@JonErlichman

[Wladek Grabinski @wladek60]

[C4P] Workshop on Open Source EDA Technologies (WOSET)
https://t.co/pv41zzXgbb
Virtual! No registration fee!
Submission Due Date: Sept 23 2024
https://t.co/L63cjBmMuQ

[mshalan @_mshalan_]

@wren6991 Hazard 3 is awesome. It will be in more chips soon 😏

[BURKOV @burkov]

Python consumes 76 times more energy and is 72 times slower than C. https://t.co/73QE1uZWwf

[mshalan @_mshalan_]

You can read more about OpenLane 2 here: https://t.co/cQs2y2l1iH
You can also jump straight into the Google Colab: https://t.co/TCVP9xS26j

[mshalan @_mshalan_]

OpenLane 2, is finally in beta. OpenLane 2 is a rewrite of OpenLane in Python that re-imagines it as not just a flow, but an infrastructure with which anyone can create a custom flow, but also, it maintains backwards compatibility with OpenLane 1. https://t.co/MFtUaFuoQ7

[Basics to ASICs Workshop @basics2asics]

The American University in Cairo is hosting a free virtual two-day training workshop on the topic entitled: “Basics to ASICs, The Open-Source Way”. For more info: https://t.co/gO7JOyZgOO
#basics2asics
#oshw
#opensource

[mshalan @_mshalan_]

After 8 transit hours at Frankfurt airport, @lufthansa delayed my flight to the next day and gave me a pillow to just sleep anywhere in the airport.

[Mohamed MK @mkkassem]

Caravel bring up day at Stanford. Go EE272B Team!!⚙️
Some are duplicates but so be it 🙂

#chipIgnite #sky130 #caravel #opensourcechips

https://t.co/Wb9YJCDGoO

[mleithy @mleithy1]

DFFRAM Compiler now running on Google Colab!
Check it out: https://t.co/s2uiguZiCv

Credits to
@proppy
for the notebook template used.
#dffram @_mshalan_ @mithro

[mshalan @_mshalan_]

@mkkassem Outstanding! A huge thank you to everyone participated to this fix!

[Mohamed MK @mkkassem]

chipIgnite one - up and running in seconds. It is using Caravel with clock mesh patch to address timing issues with metal only changes.

[mshalan @_mshalan_]

@enjoy_digital looking into adding ASIC support to LiteX starting with Sky130. Any pointers?

[mshalan @_mshalan_]

@mguthaus Do I hear “Computer Engineers”?

[mshalan @_mshalan_]

SPM clock tree (same as the one posted before) but with different CTS parameters

[mshalan @_mshalan_]

Caravel chip clock tree

[mshalan @_mshalan_]

More clock trees

[elvis @omarsar0]

🎓 A Survey on Deep Reinforcement Learning for Data Processing and Analytics

Provides a comprehensive overview of how deep reinforcement learning can improve data processing and analytics applications.

A great read for ML practitioners and students.

https://t.co/bk8Fj2f9Me

[Matthew Venn @matthewvenn]

In this interview I talk to Vladimir Milovanović about his @Google/@Skywater/@Efabless #ASIC application - a spectrometer written in Chisel. https://t.co/b1A0aNLQQA

[The Amp Hour Podcast @TheAmpHour]

This week on the show, @mkkassem of @efabless joins @Chris_Gammell to talk about building custom ASICs. They integrate many of the open source tools described in Ep 501 and are developing the OpenLANE toolflow to make it even easier!

https://t.co/XC58vIWecA