Make his finest asset yours
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@Iberia_en All of this has been done in the previous steps, it's the website that has a bug or something that doesn't let it move further, as you can see in the image it's step 2!!!! ๐ค
A major milestone in the RE of the Storey Peak board: the PCIe interface works in Gen3 x8x8 mode (with two Hard IPs), and with a custom PCIe DMA IP achieves throughput of 11 GB/s in write direction and 12 GB/s in read direction. https://t.co/4vgODxg2c4
@janmarjanovic Hey @janmarjanovic, do you have a repository with your project for the storey peak or the configuration pin file used to map this design? are you using only the hidden PCIe 8x gen3, right?
Have you asked yourself about all the details on simple components like 2FF? Recently I revisited some interesting CDC papers and wrote a post about it along with my small CDC library of components...
https://t.co/04GgUxQNXd #cdc#system_verilog#clockdomaincrossing