Architect Labs

[Architect Labs @architectlabs]

@KindredVentures 🚀

[Architect Labs @architectlabs]

Grateful to have @stevejang from @KindredVentures lead our seed. We are excited to build alongside investors who understand the full computing stack, believe deeply in the mission, and are able to look at long time horizons on where the industry is headed.

[Kindred Ventures @KindredVentures]

Architect Labs is developing AI to accelerate the co-design of custom chips - democratizing the capabilities to innovate on the hardware level of the incredible intelligence era ahead of us.

So, we’re thrilled today to share that @KindredVentures led a $24M seed round for @architectlabs, joined by @TQVentures @RaceCapital @togetherfund, as well as a storied group of operators/researchers including @snsf, @lukaszkaiser, @AravSrinivas, @tlbtlbtlb, @alexwg, and et al from @NVIDIA, @GoogleDeepMind, @OpenAI, and @perplexity_ai.

For decades, the contract between hardware and progress was simple: transistors got smaller, everything got faster, and the industry planned around the rhythm. That rhythm has slowed because of Moore’s Law stalling, and the new performance gains are coming from somewhere else entirely, architectural decisions about how memory and compute are arranged, how silicon is shaped around the workloads it serves, and how hardware and software are designed to evolve together instead of drifting apart.

AI is no longer confined to the data center. It’s running in robots, at the edge, on satellites, in every device with ambition. Each of those environments has its own physics around power, latency, and cost, and none of them are well-served by the same general-purpose GPU. The frontier labs building tomorrow's models are still optimizing upward to fit chips they didn't design, instead of designing chips downward to fit the models they imagine.

The reason that hasn't changed is not just physics, it’s also inertia. Chip design cycles remain long, manual, capital-intensive, and gated by a small population of specialists. Custom silicon has remained an inheritance of a few incumbents rather than a tool available to the new guard who need it.

Architect Labs is rebuilding that process from first principles, an AI-native, self-improving system that co-designs silicon, compilers, runtimes, and system software as a single loop, so the cadence of chip development can finally start to look like the cadence of software. It's the unlock that lets the companies shaping intelligence actually own the hardware that runs it.

The founders, @axi_master and @aadityasubedi_ understand exactly how to diagnose this problem. They have little patience for the status quo. Ebrahim started college at 15, found his way onto Apple's silicon teams, and then onto Tesla's AI5 (the custom chip behind FSD and Optimus) where he watched a piece of silicon become outdated by the models it was meant to serve before it even shipped. Aaditya was researching AI for code verification at Harvard before he and Ebrahim met at Stanford and started working on AI for chip design together, a collaboration that later became the company. Alongside them now is a stellar team, researchers and systems engineers from @Anthropic, @Google, @intel, @Meta, @Samsung and @xai, with 80+ production tape-outs and core contributions at nearly every frontier lab between them.

To the Architect Labs team, we’re honored to join you on this incredible mission! 🚀🚀🚀

[Architect Labs @architectlabs]

@chahvivi @aadityasubedi_ @axi_master grateful for your support

[Architect Labs @architectlabs]

@w1llgao so grateful for your support and the prod community!

[Architect Labs @architectlabs]

@theZachChen bullish on the chen brothers

[Architect Labs @architectlabs]

@ManiEshaan @aadityasubedi_ @axi_master thanks, grateful for your support!

[Architect Labs @architectlabs]

@021T_vc grateful for your support!

[Architect Labs @architectlabs]

@brian1zhou grateful for your support!

[Architect Labs @architectlabs]

@ekinthesumbul so excited to have @ekinthesumbul leading and shaping our journey!

[Architect Labs @architectlabs]

@sudiprokaya @aadityasubedi_ @axi_master @laminalabs thanks @sudiprokaya and @laminalabs. Explainer videos have never been faster and simplier 🚀

[Architect Labs @architectlabs]

@hsu_byron 🙏

[Architect Labs @architectlabs]

@wilsoncheung101 🚀

[Architect Labs @architectlabs]

@semiDL grateful for your support, and kind words!

[Architect Labs @architectlabs]

We share our vision for the using AI to build the next physical substrate to scale intelligence:
https://t.co/hTu03mn7KL

[Architect Labs @architectlabs]

We are proud to announce @architectlabs.

Our mission is to build an AI system that designs and provably verifies chips end-to-end. By doing so, we unlock a new era of purpose-built chips generated on demand, that powers the scale and distribution of intelligence impossible with current hardware paradigms.

Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed the first neuromorphic chip out of Intel AI Lab, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab.

We’re fortunate to be backed by investors who share our vision, including @stevejang from @KindredVentures who led our $24M seed round as well as @TQVentures , @RaceCapital , @scaletogether , @ora , and Link Ventures.

We are also grateful for the support of our angels and advisors, including @snsf, @lukaszkaiser, @AravSrinivas, Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf, @ekaurghar, @CHHubbell, Selene Casabal, @semiDL and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more.

We’ve come together to scale up and reinvent how chips are designed and provably verified end-to-end. If you want to work at the intersection of frontier AI, systems and silicon, consider joining us.

[Ebrahim H @axi_master]

Today, @aadityasubedi_ and I are excited to introduce @architectlabs.

We are building the AI system to design and provably verify chips for the world's most demanding workloads.
AI scaling is fundamentally changing the economics of hardware infrastructure. As models scale, become more capable, and more widely deployed, the bottleneck is shifting from software and models alone to the physical infrastructure that runs it: specialized compute, memory, networking, interconnects, and full-stack system design.

General-purpose hardware is no longer enough, and the world is racing to spin up new chip programs. This is not just true across datacenter training and inference, but everywhere AI enters the physical world: robotics, autonomous systems, spatial computing, defense, personal devices, industrial automation, and scientific instruments.

But designing a chip today remains one of the most gated efforts in modern technology.

A modern chip program takes years, costs hundreds of millions of dollars, and depends on a shrinking pool of expertise concentrated inside a small number of companies.

Architect Labs is a foundational lab building an AI system that designs and provably verifies chips end-to-end. We partner with semiconductor and workload companies, AI labs, and nations to turn demanding workloads into purpose-built chips, on demand at scale. We aim to drastically accelerate chip design, so that the models, software and chip designs can co-evolve together, accelerating the industry’s path to superintelligence.

Two decades ago, the fabless revolution made it possible to build a chip company without owning a fab. TSMC made world-class manufacturing available to anyone with a design. We aim to do the same for chip design itself: enable any organization with a workload, or specification, to get a purpose-built chip design that unlocks scale and distribution of intelligence impossible with current hardware paradigms.

Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed one of the first neuromorphic chips out of Intel, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab.

We have already partnered with semiconductor companies to accelerate their chip programs, and some of our AI-generated chip designs are going to tape out on leading-edge foundry nodes later this year.

We’ve also raised a $24M seed round led by @stevejang from @KindredVentures , with participation from @TQVentures , @RaceCapital , @scaletogether , @ora, and Link Ventures.

We are grateful for the support of our angels and advisors, including @snsf , @lukaszkaiser , @AravSrinivas , Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf , @ekaurghar, @CHHubbell, Selene Casabal, @semiDL , and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more.

The next great scaling law may not come from the models alone. It will come from making the physical substrate of intelligence programmable. We exist to bring this future to life.

[Architect Labs @architectlabs]

If you want to work at the frontier of AI, systems and silicon, consider joining us:
https://t.co/yBSCGqJrOt

[Architect Labs @architectlabs]

@ahsu___ 🧑‍🍳

[Architect Labs @architectlabs]

@lu__jasper 🙏

[Architect Labs @architectlabs]

Full writeup here: https://t.co/EHJWpV3Ne3

[Architect Labs @architectlabs]

Sneak peek into a project our research team has been working on.

In an experiment, we post-trained an open-source model for RTL design, using RLVR. The primary objective was to ensure functional correctness by actually compiling and simulating the Verilog. The result, Architect v0.1, matches the closed-source frontier, Claude Opus 4.6 at the time of the experiment, and beats GPT-5.4 on the non-agentic CVDP (Comprehensive Verilog Design Problems) benchmark from NVIDIA Research. In this experiment, no agent harness or test-time scaling methods were used, and rather it was to show hillclimbing using curriculum learning and reward shaping with a limited dataset.