@blip_tm LLVM does have an option to use neural networks for passes instead of hand-written heuristics, but hand-written < neural networks < LLMs writing heuristics according to this paper https://t.co/DqI0SwAtgr. Also yeah, there are always legality checks after passes
@ShashwatGoel7 Yeah I agree. A good strategy I've found, is that when someone tells you something new, you should initially buy it fully - don't fight it, and then think and question more deeply about whether you want to keep it or sell it
@ezyang One approach that we're trying is having LLMs generate kernels which are evolved, and plugging them into compilers, whose passes we evolve; works pretty well for smaller, inference chips
@shanufido@mnwsth@chipsandpol@SwarajyaMag open source formal verification frameworks like lean exist, and there have been attempts to make the same for chip design. In PnR, there’s arguably a lot more proprietary progress that comes with directly working with foundries that would be hard to replicate for EDA
@__tinygrad__ a single VLIW core or a grid? Does HDL backend mean targeting specialized architectures based on their verilog or spitting out a custom architecture?
@ShashwatGoel7@utk7arsh@iclr_conf instead of recurve self improvement (positive feedback), the clankers are engaging in self regulation (negative feedback)