Ashvin

ML hardware, compilers. Berkeley EECS ‘26

[Ashvin @ashverm4]

Made a robot that plays connect-4 against you!

[Ashvin @ashverm4]

@hapatika is this a subtweet

[Ashvin @ashverm4]

@aman_kai_sid Liked this article, particularly curious to read part 3 when it comes out!

[Ashvin @ashverm4]

@apuroop_mutyala super cool, do you have a preprint out?

[Ashvin @ashverm4]

@blip_tm LLVM does have an option to use neural networks for passes instead of hand-written heuristics, but hand-written < neural networks < LLMs writing heuristics according to this paper https://t.co/DqI0SwAtgr. Also yeah, there are always legality checks after passes

[Ashvin @ashverm4]

@blip_tm hey, sysadmin-ing in space sounds fun! You get to fly around all day, while fixing hardware

[Ashvin @ashverm4]

@bronzeagepapi any vector coprocessor?

[Ashvin @ashverm4]

@ShashwatGoel7 Yeah I agree. A good strategy I've found, is that when someone tells you something new, you should initially buy it fully - don't fight it, and then think and question more deeply about whether you want to keep it or sell it

[Ashvin @ashverm4]

@babugi28 typo?

[Ashvin @ashverm4]

@blelbach Wish I could be there! We're trying to target it with our in-house compiler, and it would've been nice to interact the folks who made it

[Ashvin @ashverm4]

@ezyang https://t.co/ZZLHhdkES3

[Ashvin @ashverm4]

@ezyang One approach that we're trying is having LLMs generate kernels which are evolved, and plugging them into compilers, whose passes we evolve; works pretty well for smaller, inference chips

[Ashvin @ashverm4]

@maharshii like this? https://t.co/giX8JtqChq

[Ashvin @ashverm4]

@shanufido @mnwsth @chipsandpol @SwarajyaMag open source formal verification frameworks like lean exist, and there have been attempts to make the same for chip design. In PnR, there’s arguably a lot more proprietary progress that comes with directly working with foundries that would be hard to replicate for EDA

[Ashvin @ashverm4]

@__tinygrad__ a single VLIW core or a grid? Does HDL backend mean targeting specialized architectures based on their verilog or spitting out a custom architecture?

[Ashvin @ashverm4]

@oznova_ I've worked through till ~chapter 8 of the PMPP book, would like this!

[Ashvin @ashverm4]

@Vicharak_In ordered :)

[Ashvin @ashverm4]

@ShashwatGoel7 @utk7arsh @iclr_conf instead of recurve self improvement (positive feedback), the clankers are engaging in self regulation (negative feedback)

[Ashvin @ashverm4]

@pauljunsukHan does it use jtag for flash and debug?

[Ashvin @ashverm4]

@apparently_sane i thought you were talking about the murakami character for a second