Chipstrat

Semis, optics/networking, physical AI, and more from @austinsemis. If you like Stratechery and SemiAnalysis, you're in the right place

[Chipstrat @chipstrat]

Advanced Packaging: Intel's EMIB vs TSMC's CoWoS
https://t.co/mgOLRmCYPS

[Semi Doped @semidoped]

Daily Update - May 29th, 2026

- a killer dashboard for learning litho by @ProbablyNoam
- TSMC price hike
- Marvell XPU >2x next year
- Synopsys 48% YoY
- Dell 🚀

https://t.co/0oSfBTStAF

[Vikram Sekar @vikramskr]

$ADI is so underdiscussed in the semi space.

Integrated Voltage Regulators are like the CPO of the power world.

The closer you are when you convert power to the chip, the more efficient it is.

[Chipstrat @chipstrat]

@IntTradeNetwork lol. 🫡 I got you!

[Chipstrat @chipstrat]

Why did $ADI agree to pay $1.5B for Empower Semi? Because XPUs are about to draw 3,000+ amps at 0.7V.
Transients and I²R both blow up.
Need to move the regulator into the substrate.
Empower headed in that direction.
And PowerLattice takes it further.
Read more here: https://t.co/hJa2XG04uZ

[Semi Doped @semidoped]

Daily Update - May 27th, 2026

- Micron, SK Hynix Reach $1 Trillion Valuation
- Infineon raises power semiconductor prices
- Semtech tops estimates, begins CopperEdge shipments

https://t.co/ZYcSaw2VfU

Semi Doped (@semidoped) is Austin Lyons (@austinsemis) of Chipstrat (@chipstrat) and Vikram Sekar (@vikramskr) of Vik’sNewsletter.

Find us on Substack, Youtube, and LinkedIn.

[Intel Foundry @Intel_Foundry]

As AI accelerators push beyond reticle limits, packaging is becoming a key scaling challenge.

A recent Chipstrat analysis highlights how Intel Foundry’s EMIB architecture can help improve scalability, yield, and cost efficiency for large AI packages.

Read here: https://t.co/rRgnjSgdGg

#IntelFoundry #Semiconductors

[Chipstrat @chipstrat]

Inside the 800G → 1.6T → 3.2T Race
Timing is everything.
What the industry said about 800G, 1.6T, 3.2T in recent earnings calls
https://t.co/lKeDuIONqA

[Semi Doped @semidoped]

Semi Doped's YouTube presence is growing.
2K subscribers strong! 💪🏽

[Semi Doped @semidoped]

Like this? Sign up today to get more Vik and Austin in your inbox daily. Free!

https://t.co/E31NVMMbFM

[Chipstrat @chipstrat]

The end of an era for VCSELs?

This post walks through:
• Why VCSELs have dominated short-reach data center optics for decades
• The problems that emerge at 200G
• Supply chain and economics

https://t.co/nIfeW60uBj

[Chipstrat @chipstrat]

Rethinking Amazon + Not All SaaS Is Dead
https://t.co/wRP19TFobz

[Semi Doped @semidoped]

Daily Update - April 30th, 2026

[Semi Doped @semidoped]

A masterclass on Google's TPU v8 Networking.
Two TPU chips? Pssh. We already knew workload-specific silicon was here.

But two scale-up networking topologies?
That's the actual Google TPU news.
Workload-specific interconnects. Think about that.

New Semi Doped with @vikramskr and @austinsemis.

Copper? Yep. Optics? Yep.

What we cover:
- TPU splits in two: 8t training, 8i inference.
- Virgo: 47 Pb/s scale-out fabric, 100% OCS.
- Boardfly scale-up: copper PCB + AECs inside racks, OCS between groups. 16 hops → 7.
- Training uses 3D torus (Rubik's Cube).
- Inference doesn't. Workload-specific topologies now.
- Dragonfly traces to a 2008 paper by Kim, Dally, Scott, Abts. Abts went on to build Groq's interconnect before Nvidia.

Chapters:
0:00 Intro
0:21 Two TPUs for two workloads
2:31 HBM, SRAM, and Axion CPUs
7:22 Why networking is the new bottleneck
17:14 Virgo: rebuilding scale-out on optics
25:24 3D torus Rubik's Cube scale-up for training 34:50 Boardfly: scale-up for MoE inference
42:07 Workload-specific everything
$GOOGL

[Chipstrat @chipstrat]

($) TSMC's Margins in Uncharted Territory

https://t.co/vBpGylUt2M

$TSM

[Austin Lyons @austinsemis]

You should think about Credo differently than you did six months ago. It's a full-stack, pure-play interconnect company spanning die-to-die, chip-to-chip, rack, and row interconnect.

With the HyperLume and Dust acquisitions, Credo gains MicroLEDs plus SiPho PIC capabilities. And a dual CPO roadmap! Not a hedge though. Laser SiPho and MicroLEDs position Credo to serve different customers; every hyperscaler runs a bespoke datacenter roadmap, and both acquisitions already come with hyperscaler customer in hand.

Moreover, Credo is running the vertical integration playbook again. Own the IP and silicon, and productize the full solution. This worked well for AECs. ZF Optics now follows that pattern with DSP + PIC in-house; ALCs follow it with DSP + MicroLEDs; OmniConnect follows it with VSR SerDes + gearbox. Good for customers (tighter co-design, ZeroFlap-class reliability, one "throat to choke"), good for Credo margins (no component margin stack paid to third parties).

Oh yeah, they acquired CoMira too. Credo already owned the PHY via its SerDes, and now Credo owns Layer 2 too with CoMira's Link-layer, ECC, and MACsec security IP; works across Credo’s scale-up and scale-out AI ambitions spanning Ethernet, ESUN, UALink and PCIe.

Quite the pure-play interconnect portfolio. $CRDO
https://t.co/EJtSkDSnZB

[Chipstrat @chipstrat]

@rob_lh China is an Interesting angle, I will add it to the backlog

[Chipstrat @chipstrat]

@Simne1core @substrate Yes, the article says as much, there is still much to do beyond technical feasibility alone

[Chipstrat @chipstrat]

X-ray lithography worked. The industry chose a different path. @substrate wants to go back. Will it work?
What about XLight, ASML, TSMC?

https://t.co/HQnzsYQDkd

[Austin Lyons @austinsemis]

It's so much fun talking with builders like Reiner. Pure dopamine for me, and I walk away smarter than I started. Interconnects for MoE, BlueSpec, Little's law. Lots of nuggets in this one.