Ivan Bunin

Kind of electronics engineer.

[Erin Catto @erin_catto]

I’m happy to announce the release of a new open source 3D physics engine called Box3D. I’ve been working on this project for a few years now, but it represents over 20 years of experience writing physics engines for games. Read more here: https://t.co/2d9aVuUsxj

[Alexander Ioffe @deusaquilus]

Architects love to say "covering indexes hurt write performance". Nobody ever has the number.

I do now.

Covering index, 2M rows, measured:
+28% INSERTs +25% UPDATEs for 1.26x faster reads.

Most of the "3x faster" story is just a broken planner.
https://t.co/TzLK1jLzUZ

I described the question to my AI → it called ExoBench → spun up a fresh Postgres, generated 200K customers and 2M orders, ran INSERTs, UPDATEs, reads, and storage measurements across three index strategies: none, single-column, and covering.

Break-even: covering only beats single-column at fewer than ~4,300 writes/min per analytical read/min. Above that, single-column wins.

The reveal: the "3.06x faster reads" you see from a covering index is mostly a measurement of how broken your planner is. Fix random_page_cost = 1.1 first and the gap shrinks to 1.26x.

Same data. Same query. Same indexes. The decision changes 10x depending on which random_page_cost your cluster is using.

Full write-up: INSERT/UPDATE/storage measurements, break-even math, and plenty of social commentary!

[Ryan Peterman @ryanlpeterman]

Marc Brooker (AWS Distinguished Eng): "The downside of caches, especially in distributed systems, is they have this mode, where the cache is empty or contains the wrong data.

The system is slow, often down, because now the backend isn't scaled to deal with all of this uncached traffic.

Customers are very disappointed and often it is down in a stable way. Like it's still it's down, but it's not going to come back up under its own energy.

Because, for example, all of this traffic is causing a huge amount of contention in my database or is saturating the network and so I can't even refill the cache. It's not even getting the right kind of data in

In general, I prefer to see the teams around me avoiding caching where possible." @MarcJBrooker

[Puneet Patwari @system_monarch]

As a Principal Engineer @Atlassian with 10+ YoE, I’ve seen rate limiting & throttling save (and break) more production services than almost any other pattern.

Interviewers have stopped asking only “Design Uber”. They now drill deep: “How do you prevent your API from melting when traffic suddenly 10x’s at 3 AM?”

These 20 must-know Rate Limiting & Throttling techniques are exactly what separates good system designs from production-ready ones that actually survive real scale.

I turned them into this full detailed thread with clear explanations and hands-on ways to master each one.

Save this thread. Read till the end.
Your next interview and your on-call rotation will thank you.

Also check out - https://t.co/Ots2nRhO5f

[Vivek Galatage @vivekgalatage]

Insightful read - Debugging Incidents in Google’s Distributed Systems

https://t.co/pC88JOfXHL

[Cameron R. Wolfe, Ph.D. @cwolferesearch]

Self-attention is the primary building block of large language models (LLMs) and transformers in general. But, how exactly does it work? 🧵 [1/8]

[Vivek Galatage @vivekgalatage]

Ultrafast Trading Systems in C++ by David Gross

"While low-latency programming is sometimes seen under the umbrella of 'code optimization', the truth is that most of the work needed to achieve such latency is done upfront, at the design phase."

https://t.co/FYv8Iml9aM

[Ivan Bunin @claylierly]

@JohanGrnvall Hi Johan! I found your page to say thank you! My whole family and I enjoy your game. Could you tell me if I can donate something extra to show my gratitude, or maybe even contribute to the game's development or even a new game from you?

[Dustin Getz @dustingetz]

https://t.co/EsGPxWIAUM

[QAD | THE JON @THEJON07]

Combo challenge for everyone. Perform this combo on any female character.

[Ivan Bunin @claylierly]

@blelbach And this Python DSL will look exactly like C?

[Jeff Dean @JeffDean]

Main lore around the origin of MapReduce was that we were rewriting our indexing pipeline for the search system, and we realized that lots of the different phases were conceptually simple but required large scale processing (extract link text from each page, identify language for each page, compute checksum of contents to identify duplicates, etc). Each phase needed to be parallelized, made robust to machine failures, etc. Squinting at each of the phases we came up with MapReduce as an abstraction where we could have an implementation that would do all the complex work under the abstraction boundary, and where the expression of the operations could be nice and simple.

[Alexandre Borges @ale_sp_brazil]

I am pleased to announce the publication of the sixth article in the Exploiting Reversing Series (ERS).

Titled "A Deep Dive Into Exploiting a Minifilter Driver (N-day)", this 251-page article provides a comprehensive look at a past vulnerability in a mini-filter driver:

https://t.co/Sh8pgB4bh8

It guides readers through the entire investigation process—beginning with binary diffing and moving through reverse engineering, deep analysis and proof-of-concept stages into full exploit development.

I hope this serves as a valuable resource for your research. If you enjoy the content, please feel free to share it or reach out with feedback.

Have an excellent day!

[Strace @straceX]

https://t.co/5ht7WDcLVo

[Alexandre Borges @ale_sp_brazil]

Interesting discussion:

Modern C++ Firmware: Proven Strategies for Tiny, Critical Systems:

Part 01: https://t.co/bSiHyYc3HO
Part 02: https://t.co/ZRME43Y2Ir
Part 03: https://t.co/ZRlgNLb8xi
Part 04: https://t.co/Yp5O89Bmjs
Part 05: https://t.co/1XvYajpXXw
Part 06: https://t.co/bc754IiG8s
Part 07: https://t.co/dRpC9hjAt6
Part 08: https://t.co/ZtksK0LbMg
Part 09: https://t.co/7eMG4rc475

#programming #firmware #cpp

[Steve the Beaver @beaversteever]

Software is dead.

I've posted this before but here's what I'd do now

1. Digital electronics
- you need to understand what a flop is
- boolean logic and k-maps
- metastability
- memory
- finite state machines
- timing diagrams (setup/hold, propagation delay)
- synchronous vs asynchronous design
- combinational vs sequential logic
- clock domains and clock domain crossing
Resources:
- "Digital Design and Computer Architecture" by Harris & Harris
- nandland basics

2. Verilog / Hardware Description Languages
- modules, ports, signals
- continuous assignment vs procedural assignment
- blocking vs non-blocking assignment
- sensitivity lists
- RTL coding discipline (synthesizable subset)
- testbenches and simulation
- structural vs behavioral descriptions
Resources:
- "FPGA Prototyping by Verilog Examples" by Pong Chu
- nandland Verilog tutorials
- HDLBits (online practice problems)

3. Computer architecture
- datapaths and control paths
- registers, ALUs, multiplexers
- pipelines and hazards
- microcoded vs hardwired control
- instruction sets and decoding
- caches and memory hierarchies
- buses and interconnects
Resources:
- "Computer Organization and Design" by Patterson & Hennessy
- "Computer Architecture: A Quantitative Approach" by Hennessy & Patterson

4. FPGA architecture
- LUTs, flip-flops, carry chains
- block RAM and distributed RAM
- DSP slices and multipliers
- clocking resources (MMCMs, PLLs)
- IO blocks and SERDES
- resource utilization and constraints
Resources:
- Vendor user guides (Xilinx)
- nandland FPGA
- FPGA4Fun tutorials

5. Toolchain & workflow
- synthesis -> place & route -> bitstream
- constraint files (timing, pin mapping, clock definitions)
- timing closure and static timing analysis
- simulation before synthesis
- debugging with waveform viewers and ILAs

6. System design
- finite state machine design methodology
- streaming vs memory-mapped architectures
- interfacing with peripherals (UART, SPI, I2C, Ethernet)
- DMA and buffering
- soft CPUs (MicroBlaze, Nios II, RISC-V)
- system buses (AXI, AHB, Wishbone)
Resources:
- Xilinx AXI IP examples in Vivado

7. Hardware/software co-design
- partitioning work between FPGA logic and embedded CPU
- hardware accelerators for software bottlenecks
- co-simulation and HW/SW debug
- real-time constraints
Resources:
- Zynq SoC tutorials (Xilinx)
- “Designing Embedded Systems with FPGA” by Peter Athanas et al.

8. Mindset shift
- hardware is parallel, not sequential
- time is in cycles
- resources are physical

[Vivek Galatage @vivekgalatage]

eBPF interactive learning!

https://t.co/qFdveeJShs

[Vivek Galatage @vivekgalatage]

Quite interesting read

https://t.co/a6wrDd5Mdp

[Md Ismail Šojal 🕷️ @0x0SojalSec]

This Google Collab notebooks to implement every Machine Learning Algorithm from scratch🤯

- https://t.co/ngbtQvCQos

and this is free

[Lior Alexander @LiorOnAI]

Ilya Sutskever (OpenAI cofounder) top 30 must-read research papers.

"If you really learn all of these, you’ll know 90% of what matters today"