Today at 3:30PM PT at PLDI: Rupicola, my thesis project! Come by (or join us virtually!) to learn about building domain-specific compilers that generate efficient C code from functional programs, with proofs🐓☑️. Paper (OA): https://t.co/IWWKRgg9SY, Code: https://t.co/NKTvCiOz5R
I got a job and I'm moving! I'll be joining the faculty of @ICepfl in Lausanne, Switzerland next year. I'm very excited and humbled to be joining such a great department, and I look forward to working with many awesome students and all my peers at @EPFL_en and beyond.
@PDVLcc :) Thanks! Generating the C++ models takes (mostly) linear time in the size of the designs, so ≈ 0 for our examples. Compiling the C++ at -O3 can take time (a few seconds per 10ksloc?); -O2 is faster (the models are decently compact and they don't tend to trip GCC).
I just presented Cuttlesim 🦑 at ASPLOS 2021 :) Cuttlesim is a new simulator and debugger for our rule-based hardware design language, Kôika. In a 🥜🐚: you can get much faster simulation and much nicer debugging by *not* compiling to Verilog. https://t.co/UW0lfYYjCr
Just released! Alectryon is a literate programming toolkit for Coq and also a compiler from Coq documents to interactive webpages. Blog post at https://t.co/cnTtEbi89s, repo at https://t.co/rYYQf2dOGD, and academic paper at https://t.co/jIQbIj3u7X— come to the SLE talk tomorrow!
My lab has a new blog! The focus is on our research, so lots of Coq proofs, systems, and compilers, a bit of hardware, and some tutorials and even guest posts! Right now we have Coq tips, a guide on captioning talk videos, and an Iris intro. https://t.co/ILmIMt2mDa ✍️🐓✅
Our IJCAR2020 paper just got published! https://t.co/sjq4cwh3Aw. We show how to build flexible & verified domain-specific compilers, with an emphasis on performance, to get end-to-end proofs connecting high-level mathematical descriptions to assembly. The talk is on Wednesday.
Our PLDI 2020 paper is out! We present a formal semantics and a verified compiler for Kôika🦑, a new rule-based hardware language. To evaluate it, we wrote performance proofs and ran a small #RISCV core on FPGA. Check it out at https://t.co/cIzXeHHWWN & https://t.co/QUcaWsJN0W