Deric Pang

research @architectlabs. previously @figma, @google, @uwnlp.

[Deric Pang @deric_pang]

@lu__jasper could've just told me you thought my website was ugly instead of tweeting this btw

[Deric Pang @deric_pang]

@benhylak the goat fr

[Jasper Lu @lu__jasper]

Taking a short break from LLM research to go back to my roots.

Introducing... Concept Lenses! A training-free way to do similarity search along whatever concept you care about.

Typically, embedding-based similarity search is constrained by whatever notion of similarity the model learned in training. This means that if the model is primed for semantic similarity, but you actually care more about visual appearance, you'd need to switch models.

Under a Concept Lens projection, though, distance between embeddings means distance only along the concept you care about.

Blog post: https://t.co/aO36RaATpT
Demo: https://t.co/cM9ySdHvW4

[kache @yacineMTB]

"founding MTS" 💀 bro you're a wagie

[Jasper Lu @lu__jasper]

Sharing my first of hopefully many research blog posts! https://t.co/qPvLWmsghr

This one is the kind of educational blog post I wish I'd had when I started with RL for LLMs.

I tried to make it as open as possible. Every rollout is browsable, the code is open source, and I walk through my entire thought process, from learning rate sweeps to reward shaping.

[Jasper Lu @lu__jasper]

Congrats to the folks at Architect Labs for hitting this milestone!

[Deric Pang @deric_pang]

@cryingpotat0 @nvidia

[Deric Pang @deric_pang]

In college, I got an internship at @nvidia by building a self-driving robot car with a raspberry pi, a breadboard + motor from amazon, and the cheapest sensors I could find at the time. Wish something like this was around back then! Super excited to build with this.

[clem 🤗 @ClementDelangue]

https://t.co/KXKqDSkNJj

[Lukasz Kaiser @lukaszkaiser]

The future of hardware and software co-design will be wild.

[Adrian @ahsu___]

Introducing Project Redwood 🚀🚀

@architectlabs is a frontier AI lab bringing together talent from Anthropic, xAI, Google DeepMind, and seasoned leaders across the hardware industry. We've raised a $24M seed round to build AI systems for chip design.

我們 Architect Labs 是一個 frontier AI lab ，由各家 Anthropic, xAI, Google DeepMind 還有各種硬體專家們組成，我們在做的是 ai system for chip design，目前募資 seed round $24M
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Today, every major hardware company has its own chip design workflow—but these organizations and processes have become so large and entrenched that truly revolutionary change is difficult. We’re starting from first principles to create an AI-native chip design workflow—one that enables chip development to finally move at the speed of AI.

現在每家大硬體巨頭都有自己的晶片設計流程，但很多都大到不能做革命性的流程改動；我們在做的是從零思考，創造 ai native 的晶片設計流程，讓晶片設計真正跟上 AI 的速度。
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Project Redwood - from a single specification, our AI system designed, verified, and deployed a chip in under two weeks—delivering 3.4× better performance per watt than NVIDIA Jetson on billion-parameter models including Llama, Qwen, and Kimi. It autonomously generated the RTL, verification, firmware, drivers, and kernels, co-designing the model, software, and silicon in one optimization loop. We acknowledge that silicon is the ultimate ground-truth. We’re taking our approach all the way to GDS. We intend to tape-out multiple improved families of Redwood co-designed for various use-cases, on TSMC.

Project Redwood - 一份規格書，我們的 AI 系統在兩週內完成晶片的設計、驗證與部署。在 Llama、Qwen 和 Kimi 等模型，其 performance per watt 比 NVIDIA Jetson 高出 3.4 倍。從 RTL、驗證、韌體、驅動到核心 kernels，全部由 AI 自己寫，並在同一個 loop 中自主設計模型、軟體與晶片。當然，流片才是最終的驗證標準。因此，我們會將這套方法一路推進至 GDS，並計畫採用台積電製程，針對不同應用場景協同設計多個持續改良的 Redwood 晶片系列並完成流片。
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Full report on Redwood architecture and its autonomous design. Follow @architectlabs on X

我們有公開 Redwood 架構及其自主設計流程，歡迎去看論文～

[Architect Labs @architectlabs]

Full report on Redwood architecture and its autonomous design: https://t.co/Xnecf1eEEv

[bubble boi @bubbleboi]

WHAT

[Deric Pang @deric_pang]

a glimpse of what we're doing at @architectlabs!

[Architect Labs @architectlabs]

We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.

It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.

From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.

Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.

[Deric Pang @deric_pang]

Excited to share what I've been working on for the past few months! We have an amazing team and are doing really interesting work at the intersection of frontier AI and chip design.

[Ebrahim H @axi_master]

Today, @aadityasubedi_ and I are excited to introduce @architectlabs.

We are building the AI system to design and provably verify chips for the world's most demanding workloads.
AI scaling is fundamentally changing the economics of hardware infrastructure. As models scale, become more capable, and more widely deployed, the bottleneck is shifting from software and models alone to the physical infrastructure that runs it: specialized compute, memory, networking, interconnects, and full-stack system design.

General-purpose hardware is no longer enough, and the world is racing to spin up new chip programs. This is not just true across datacenter training and inference, but everywhere AI enters the physical world: robotics, autonomous systems, spatial computing, defense, personal devices, industrial automation, and scientific instruments.

But designing a chip today remains one of the most gated efforts in modern technology.

A modern chip program takes years, costs hundreds of millions of dollars, and depends on a shrinking pool of expertise concentrated inside a small number of companies.

Architect Labs is a foundational lab building an AI system that designs and provably verifies chips end-to-end. We partner with semiconductor and workload companies, AI labs, and nations to turn demanding workloads into purpose-built chips, on demand at scale. We aim to drastically accelerate chip design, so that the models, software and chip designs can co-evolve together, accelerating the industry’s path to superintelligence.

Two decades ago, the fabless revolution made it possible to build a chip company without owning a fab. TSMC made world-class manufacturing available to anyone with a design. We aim to do the same for chip design itself: enable any organization with a workload, or specification, to get a purpose-built chip design that unlocks scale and distribution of intelligence impossible with current hardware paradigms.

Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed one of the first neuromorphic chips out of Intel, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab.

We have already partnered with semiconductor companies to accelerate their chip programs, and some of our AI-generated chip designs are going to tape out on leading-edge foundry nodes later this year.

We’ve also raised a $24M seed round led by @stevejang from @KindredVentures , with participation from @TQVentures , @RaceCapital , @scaletogether , @ora, and Link Ventures.

We are grateful for the support of our angels and advisors, including @snsf , @lukaszkaiser , @AravSrinivas , Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf , @ekaurghar, @CHHubbell, Selene Casabal, @semiDL , and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more.

The next great scaling law may not come from the models alone. It will come from making the physical substrate of intelligence programmable. We exist to bring this future to life.

[Ebrahim H @axi_master]

Today, @aadityasubedi_ and I are excited to introduce @architectlabs.

We are building the AI system to design and provably verify chips for the world's most demanding workloads.
AI scaling is fundamentally changing the economics of hardware infrastructure. As models scale, become more capable, and more widely deployed, the bottleneck is shifting from software and models alone to the physical infrastructure that runs it: specialized compute, memory, networking, interconnects, and full-stack system design.

General-purpose hardware is no longer enough, and the world is racing to spin up new chip programs. This is not just true across datacenter training and inference, but everywhere AI enters the physical world: robotics, autonomous systems, spatial computing, defense, personal devices, industrial automation, and scientific instruments.

But designing a chip today remains one of the most gated efforts in modern technology.

A modern chip program takes years, costs hundreds of millions of dollars, and depends on a shrinking pool of expertise concentrated inside a small number of companies.

Architect Labs is a foundational lab building an AI system that designs and provably verifies chips end-to-end. We partner with semiconductor and workload companies, AI labs, and nations to turn demanding workloads into purpose-built chips, on demand at scale. We aim to drastically accelerate chip design, so that the models, software and chip designs can co-evolve together, accelerating the industry’s path to superintelligence.

Two decades ago, the fabless revolution made it possible to build a chip company without owning a fab. TSMC made world-class manufacturing available to anyone with a design. We aim to do the same for chip design itself: enable any organization with a workload, or specification, to get a purpose-built chip design that unlocks scale and distribution of intelligence impossible with current hardware paradigms.

Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed one of the first neuromorphic chips out of Intel, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab.

We have already partnered with semiconductor companies to accelerate their chip programs, and some of our AI-generated chip designs are going to tape out on leading-edge foundry nodes later this year.

We’ve also raised a $24M seed round led by @stevejang from @KindredVentures , with participation from @TQVentures , @RaceCapital , @scaletogether , @ora, and Link Ventures.

We are grateful for the support of our angels and advisors, including @snsf , @lukaszkaiser , @AravSrinivas , Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf , @ekaurghar, @CHHubbell, Selene Casabal, @semiDL , and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more.

The next great scaling law may not come from the models alone. It will come from making the physical substrate of intelligence programmable. We exist to bring this future to life.

[Architect Labs @architectlabs]

Sneak peek into a project our research team has been working on.

In an experiment, we post-trained an open-source model for RTL design, using RLVR. The primary objective was to ensure functional correctness by actually compiling and simulating the Verilog. The result, Architect v0.1, matches the closed-source frontier, Claude Opus 4.6 at the time of the experiment, and beats GPT-5.4 on the non-agentic CVDP (Comprehensive Verilog Design Problems) benchmark from NVIDIA Research. In this experiment, no agent harness or test-time scaling methods were used, and rather it was to show hillclimbing using curriculum learning and reward shaping with a limited dataset.

[Tom Duncalf @tomduncalf]

Very excited that Figma Make is available for everyone as of today! Go check it out and let me know your thoughts :)