f4pga

[CHIPSAlliance @CHIPSAlliance]

This year in @GoogleOSS Summer of Code, we welcome 8 contributors who are being introduced to the @CHIPSAlliance community & mentors. Learn about projects that push for #opensource #hardware, #ASIC & #FPGA design: https://t.co/Vg35q0TrSe @antmicro @f4pga @OpenROAD_EDA #GSoC2023

[CHIPSAlliance @CHIPSAlliance]

The next #GSOC2023 project is to expand the #opensource @f4pga toolkit utilization in #Makerchip's Virtual FPGA Lab environment. Use your #Python and #FPGA dev skills to help add more FPGA targets to the Virtual FPGA Lab: https://t.co/GZTF25Wg6t @GoogleOSS @SteveHoover99 #GSoC

[CHIPSAlliance @CHIPSAlliance]

Final call today for this year's @Google Summer of Code contributor applications. Sign up by 18:00 UTC to put your skills to use in real #opensource #hardware, #ASIC & #FPGA projects: https://t.co/apWwPONXT9 @GoogleOSS #GSoC2023 @antmicro @mithro @SaliganeMehdi @OpenROAD_EDA

[CHIPSAlliance @CHIPSAlliance]

We're expanding our #FPGA tool profiling platform by developing a web-based performance visualization tool. Join #GSOC2023 and use your #Python, #UX & #JavaScript skills to help us visualize, compare and optimize FPGA toolchain performance: https://t.co/MaU5OXHuFB @GoogleOSS

[CHIPSAlliance @CHIPSAlliance]

Join @F4PGA efforts toward a more open #FPGA ecosystem by documenting the #Spartan6 bitstream and contribute to extending #opensource toolchains on new platforms with your #Python & #Verilog skills. Interested? Sign up for #GSoC 2023: https://t.co/Tmq3GDcR5J @GoogleOSS @antmicro

[CHIPSAlliance @CHIPSAlliance]

Applications for #GSOC2023 contributors start today! Work with us on projects involving @OpenROAD_EDA, #Verilog, #OpenFASOC, @f4pga toolchain & more to help us advance #opensource #hardware, #ASIC & #FPGA design: https://t.co/PFlGuaL2I7
@GoogleOSS @mithro @antmicro @SaliganeMehdi

[CHIPSAlliance @CHIPSAlliance]

Another #GSoC project idea involves documenting the XADC and the DNA_PORT blocks for the @AMD @XilinxInc 7-series #FPGAs, making them available in the @F4PGA #opensource flow. Sounds interesting? Become a contributor:
https://t.co/LiJevDGFuH
@GoogleOSS @antmicro #Verilog

[CHIPSAlliance @CHIPSAlliance]

Are you passionate about digital signal processing & #FPGA hardware design? Join us for #GSoC to work on integrating DSP hard blocks in @F4PGA. Sign up by April 4, gain valuable experience and shape the future of open #ASIC/FPGA flows: https://t.co/WZC09DGRo5 @antmicro @googleoss

[CHIPSAlliance @CHIPSAlliance]

If you're interested in advancing #FPGA with #opensource, sign up for #GSoC this April! Help us improve tools like FPGA Database Visualizer to better understand the internal structure of specific FPGAs: https://t.co/vZ6Br00uSB
@GoogleOSS @CHIPSAlliance @antmicro @f4pga

[CHIPSAlliance @CHIPSAlliance]

CHIPS is excited to be back as a mentor organization in this year's @Google Summer of Code. Join our mission to push forward #opensource #hardware, #ASIC & #FPGA design. Check out our project ideas: https://t.co/apWwPOOvIH #GSoC2023 @GoogleOSS @antmicro @mithro @saliganemehdi

[Antmicro @antmicro]

Learn about the latest developments in #opensource #SystemVerilog/UVM support in #Verilator, as we’re moving one step closer to the next significant milestone - running the first SV UVM testbench through Verilator: https://t.co/aYgOwneQu7
@CHIPSAlliance @westerndigital

[Antmicro @antmicro]

Don't miss the latest updates about #opensource verification using #Verilator from Antmicro. Join the discussion about #Verilator v5 and UHDM #SystemVerilog frontend at the @Google hosted @chipsalliance Tech Update. Register now: https://t.co/5u6MEw8CzR @GoogleOSS @westerndigital

[CHIPSAlliance @CHIPSAlliance]

Join the CHIPS Alliance Fall Technology Update hosted by @Google for talks on collaborative #ASIC and #FPGA development by @Microsoft (#Caliptra), @intel, @antmicro, @ZephyrIoT, @GlobalFoundries, @efabless & more, following #RISCVSummit. Register: https://t.co/BfynowiJ7J @risc_v

[CHIPSAlliance @CHIPSAlliance]

CHIPS Alliance is a sponsor of the #RISCVSummit. Meet us & the @antmicro team at booth T1 to talk about #opensource collaborative HW development, and join us a day later at the CHIPS Alliance Fall Technology Update at @Google: https://t.co/BfynowAkwj @risc_v @linuxfoundation

[Antmicro @antmicro]

Our recent project within @CHIPSAlliance @f4pga group involves a new #Python build system & unified f4pga CLI tool, allowing us to wrap the underlying tools into a single CLI, making F4PGA a more complete toolchain: https://t.co/jCdZJDJhyV @XilinxInc @QuickLogic_Corp @latticesemi

[Antmicro @antmicro]

And our final talk at #ZephyrDevSummit this year starts at 12:00 PM! Learn about #ZephyrRTOS in an #ML-oriented #UltraScale+ based data processing platform utilizing the #NVMe interface by Antmicro & @westerndigital https://t.co/JPggHVZc6m @ZephyrIoT @XilinxInc @f4pga

[Antmicro @antmicro]

If you’re at this year's #ZephyrDevSummit, visit Antmicro at booth B5! Take the chance to ask your questions about SW/HW co-development with @renodeio, #ZephyrRTOS for #FPGAs & our software-driven approach. https://t.co/TKHV7aBSd1. @ZephyrIoT @risc_v @f4pga @CHIPSAlliance

[Antmicro @antmicro]

At this year's #ZephyrDevSummit, we will talk about using #ZephyrRTOS to execute #ML and other time-critical workloads on an #UltraScale+ based data processing platform via #NVMe, developed by @antmicro and @westerndigital: https://t.co/JPggHVHBeO. @ZephyrIoT @XilinxInc @f4pga

[f4pga @f4pga]

As part of #GSoC this year, Lucca Silva will work on creating a smart & cloud based infrastructure for testing analog blocks functionality in #OpenFASOC by leveraging @GoogleCloud. Read more:
https://t.co/C5kNWQM7XW @GoogleOSS @CHIPSAlliance @OpenROAD_EDA @SaliganeMehdi

[f4pga @f4pga]

Karim Tera is another contributor who'll be joining us for this year's #GSoC #GoogleSummerOfCode, to work on creating a #systemverilog preprocessor for #Verible. Read more about his project: https://t.co/praYQzB3aL @GoogleOSS @CHIPSAlliance @antmicro