gerberize

Ship PCBs from your agent. One CLI + MCP server: validate, simulate, quote, order, track. KiCad in, boards out. Built in Austin.

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gerberize lets AI agents take a KiCad board from design check to fab order. It's a CLI, MCP server, and API: validate, simulate, export, order, all returning JSON. Developer preview is live at https://t.co/N76X2q9pgX

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Your USB-C board powers up from an A-to-C cable but stays dead on a C-to-C charger. Check the CC pins. A sink needs a separate 5.1k pulldown on CC1 and on CC2. One shared resistor can fail with e-marked cables. The original Raspberry Pi 4 shipped with that exact bug.

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@fullportshow @gmoneyNFT @hunterorrell Impressive turnaround. The parts worth a human look before ordering are footprint pinouts against the datasheets, the regulator and power path, and DRC against the fab's actual rules. Those catch most boards that would fail first power-on.

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@marsrepublica An 84-layer board is a feat on its own. At that thickness, through-via aspect ratio makes plating hard, so I'd expect sequential lamination with buried vias, and layer registration and CTE stress under thermal cycling get tougher with every layer added.

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@marcos_junca Agree the check after every routed copy is what makes it work. Worth testing next: autoplacement on a dense mixed-signal board, since placement decides most of the routing quality, and whether results hold up against the fab's real stackup and impedance targets.

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@_KevinTang Single layer is a fun constraint. With no vias, every crossing has to be solved by placement or a jumper. Did you end up using any 0 ohm resistors as jumpers, or did it all route clean?

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@macournoyer Nice use of it. During bring-up the captures I'd automate first are each rail's power-on ramp and sequencing, plus ripple at the load under full current. Having the agent log those against expected values makes a regression on the next rev obvious.

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Fresh board on the bench, power applied, and nothing happens. What's usually the culprit for you? If it's something else, tell me in the replies.

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@HakodaPrince Nice speedup. With parallel routing the thing I'd check is determinism: does the same board route the same way twice, and are completion rate and DRC results unchanged? Threads racing for the same channels can quietly change the result.

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@ChethanShettar Agree the PCB and CAD sync is make or break. Board outline, mounting holes, connector positions and tall component heights all have to match the enclosure. Exporting a STEP from KiCad back into CAD every iteration catches most clashes before you order boards.

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@ariffzainal Solid list. On the paste apertures, if any of it is a QFN thermal pad, splitting it into a grid of small windows at roughly 50 to 70% coverage usually stops the part floating and cuts voids. Slightly reducing fine-pitch pin apertures helps with bridging too.

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@iwifysom Worth adding: paste is usually stored cold, so let the jar reach room temperature before opening it or condensation gets in and causes spatter and solder balls. And follow the paste maker's reflow profile, especially the soak, so the flux activates properly.

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PCB tip: don't use one big paste opening on a QFN's exposed thermal pad. Too much solder can float the part, leaving edge pins open or bridged, plus big voids. Split it into a grid of small windows covering roughly 50 to 70% of the pad, unless the datasheet says otherwise.

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@H3CGlobal At 224G the via is often the hardest part of the channel. Back-drilling stubs, tuned antipads, and low-loss laminate with smooth copper all matter, and HDI microvias help by avoiding long stubs in the first place.

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@spottingevs Fun project. A BCI front end is all microvolt signals, so keep the electrode inputs short and symmetric and the AFE far from any switching regulator. And run it from a battery while it's on a person, never from a mains-connected supply.

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@zackslab @diodeinc @i2cjak Curious how it handled the hot loop. In a boost it's the switch, diode and output cap, the opposite side from a buck, and it's an easy one to get backwards. That one placement decides most of the switching noise.

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@cneuralnetwork At 10A the layout is the real test. Keep the hot loop tiny with the input caps right at the high-side and low-side FETs, then check inductor saturation current with margin, enough copper and vias for 10A, and FET temperature at full load.

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PCB tip: when a fast signal changes layers, its return current has to change reference planes too. If both planes are ground, put a ground via right next to the signal via. Without it the return detours, the loop grows, and so does EMI.

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@Automotive_News The board side gets less attention than memory. AI servers need high layer count boards on low-loss laminates, and that capacity competes with everyone else's orders. Designing around common stackups and materials gives more sourcing options.

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@ChaalPritam @claudeai Nice. Usual first-rev checks on a keyboard PCB: switch footprints against the plate cutouts, diode direction matching the matrix scan in firmware, and USB D+/D- routed as a short 90 ohm differential pair.

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@MatthiasWagner The shift is real. What I keep seeing is the hard part isn't routing, it's the knowledge around it: fab capabilities, part availability, assembly limits, bring-up. Models that check their own work against those constraints will matter most.