#IVerilog - Twitter Hashtag

Z80でCP/MとかFUZIXとか

@DragonBallEZ

13 days ago

サンプルソースの波形が出たw🤔 #iVerilog #FPGA

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Logic Destroyer

@splinedrive

over 3 years ago

#OpenAIChatGPT helped mit to generate a script to download the latest zipped tarball of oss-cad-suite from @YosysHQ to have the latest opensource eda #toolchains on my x64 linux sytem, feel free to make your life easier! #verilog #iverilog #verilator #ice40 #ecp5 #lattice #fpga

splinedrive's tweet photo. #OpenAIChatGPT helped mit to generate a script to download the latest zipped tarball of oss-cad-suite from @YosysHQ to have the latest opensource eda #toolchains on my x64 linux sytem, feel free to make your life easier!
#verilog #iverilog #verilator #ice40 #ecp5 #lattice #fpga https://t.co/oxwUm9yPYD

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Marcelo Samsoniuk

@samsoniuk

almost 4 years ago

#DarkRISCV easy way: just git it from https://t.co/qISEGAQJII, enter in the sim directory and run make! you need #iverilog in the path and, case you have #gtkwave, you can use the VCD file and see the 3-stage pipeline working! ❤️

samsoniuk's tweet photo. #DarkRISCV easy way: just git it from https://t.co/qISEGAQJII, enter in the sim directory and run make! you need #iverilog in the path and, case you have #gtkwave, you can use the VCD file and see the 3-stage pipeline working! ❤️ https://t.co/3jEX6rjBCs

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Logic Destroyer

@splinedrive

almost 4 years ago

#fpgafriday time for new #yosys #oss-cad-suite-build #iverilog #verilator #openfpgaloader #gtkwave.....https://t.co/zTOozc09Lt 💥💥💥💯💯❤️💯💥❤️❤️❤️❤️❤️❤️❤️💯💥💥💯💥💥💥💥❤️❤️💯❤️❤️💯❤️❤️💯❤️😕

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Logic Destroyer

@splinedrive

almost 4 years ago

Without EDA the logic designer would be a loser! Bless the EDA developers and researchers! #fpga #asic #verilog #vhdl #yosys #xilinx #altera #lattice #gowin #anlogic #simulation #logicDesign #gates #and #or #nand #nor #inv #dff #comb #gtkwave #iverilog #vivado #synopsys #mentor

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Logic Destroyer

@splinedrive

almost 4 years ago

without sv2v I couldn't use #iverilog #icarus ... my #systemverilog is to hard for it! https://t.co/vQCFj7hKMp

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Logic Destroyer

@splinedrive

almost 4 years ago

Which verilog simulator is your choice? #vivado #iverilog #gtkwave #modelsim #verilator #verilog #logic #design #fpga #asic

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Logic Destroyer

@splinedrive

over 4 years ago

Wow is the first time I use #verilator for simulation. Is so fast...with #iverilog it would take 1 day to simulate #riscv #kianRiscV cpu. I have reworked the mem interface and the cpu statemachine. Now I have a tool to come forward.. Generates c++, I like it

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Logic Destroyer

@splinedrive

over 5 years ago

Implemented #i2c #master from scratch on #ice40 #fpga. PoC is #ds3231 #rtc. 400k/bit #fastmode transfer. Displaying hours, minutes and seconds via #8bit #leds #bcd encoded. I like #2wire #protocol. Thanx to #icefun, #yosys, #iverilog, #nextpnr and #gtkwave #opensource 💪

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Le Dahu @realCWolpert

over 5 years ago

Simulation of SPI Master sending last 256 byte from ice40 BRAM to SPI/USB bridge. #Yosys, #iverilog and #GTKWave on #Linux - free and open source, made by awesome people. My friends were sceptical but I like the toolchain a lot (haven't really tried icecube and modelsim, no need)